From owner-svn-src-head@FreeBSD.ORG Sat Apr 27 23:07:52 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by hub.freebsd.org (Postfix) with ESMTP id 52EFF159; Sat, 27 Apr 2013 23:07:52 +0000 (UTC) (envelope-from wkoszek@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 2EAD11E5D; Sat, 27 Apr 2013 23:07:52 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.6/8.14.6) with ESMTP id r3RN7p4t007743; Sat, 27 Apr 2013 23:07:51 GMT (envelope-from wkoszek@svn.freebsd.org) Received: (from wkoszek@localhost) by svn.freebsd.org (8.14.6/8.14.5/Submit) id r3RN7ouh007734; Sat, 27 Apr 2013 23:07:50 GMT (envelope-from wkoszek@svn.freebsd.org) Message-Id: <201304272307.r3RN7ouh007734@svn.freebsd.org> From: "Wojciech A. Koszek" Date: Sat, 27 Apr 2013 23:07:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r249999 - in head: share/man/man4/man4.arm sys/arm/arm sys/arm/include sys/dev/mmc sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 27 Apr 2013 23:07:52 -0000 Author: wkoszek Date: Sat Apr 27 23:07:49 2013 New Revision: 249999 URL: http://svnweb.freebsd.org/changeset/base/249999 Log: Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port. Submitted by: Thomas Skibo Tested by: wkoszek (ZedBoard) Reviewed by: wkoszek, freebsd-arm@ (no objections raised) Added: head/share/man/man4/man4.arm/devcfg.4 (contents, props changed) Modified: head/share/man/man4/man4.arm/Makefile head/sys/arm/arm/cpufunc.c head/sys/arm/arm/identcpu.c head/sys/arm/include/armreg.h head/sys/dev/mmc/mmc.c head/sys/dev/uart/uart.h head/sys/dev/uart/uart_bus_fdt.c Modified: head/share/man/man4/man4.arm/Makefile ============================================================================== --- head/share/man/man4/man4.arm/Makefile Sat Apr 27 22:47:52 2013 (r249998) +++ head/share/man/man4/man4.arm/Makefile Sat Apr 27 23:07:49 2013 (r249999) @@ -1,6 +1,6 @@ # $FreeBSD$ -MAN= mge.4 npe.4 +MAN= mge.4 npe.4 devcfg.4 MLINKS= mge.4 if_mge.4 MLINKS+=npe.4 if_npe.4 Added: head/share/man/man4/man4.arm/devcfg.4 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/share/man/man4/man4.arm/devcfg.4 Sat Apr 27 23:07:49 2013 (r249999) @@ -0,0 +1,84 @@ +.\" +.\" Copyright (c) 2013 Thomas Skibo +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. The name of the author may not be used to endorse or promote products +.\" derived from this software without specific prior written permission. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd February 28, 2013 +.Dt DEVCFG 4 +.Os +.Sh NAME +.Nm devcfg +.Nd Zynq PL device config interface +.Sh SYNOPSIS +.Cd device devcfg +.Sh DESCRIPTION +The special file +.Pa /dev/devcfg +can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000. +.Pp +On the first write to the character device at file offset 0, the devcfg driver +asserts the top-level PL reset signals, disables the PS-PL level shifters, +and clears the PL configuration. Write data is sent to +the PCAP (processor configuration access port). When the PL asserts the +DONE signal, the devcfg driver will enable the level shifters and release +the top-level PL reset signals. +.Pp +The PL (FPGA) can be configured by writing the bitstream to the +character device like this: +.Bd -literal -offset indent +cat design.bit.bin > /dev/devcfg +.Ed +.Pp +The file should not be confused with the .bit file output by the FPGA +design tools. It is the binary form of the configuration bitstream. +The Xilinx +.Pa promgen +tool can do the conversion: +.Bd -literal -offset indent +promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin +.Ed +.Sh SYSCTL VARIABLES +The devcfg driver provides the following +.Xr sysctl 8 +variables: +.Bl -tag -width 12 +.It Va hw.fpga.pl_done +.Pp +This variable always reflects the status of the PL's DONE signal. A 1 +means the PL section has been properly programmed. +.It Va hw.fpga.en_level_shifters +.Pp +This variable controls if the PS-PL level shifters are enabled after the +PL section has been reconfigured. This variable is 1 by default but setting +it to 0 allows the PL section to be programmed with configurations that +don't interface to the PS section of the part. Changing this value has no +effect on the level shifters until the next device reconfiguration. +.Sh FILES +/dev/devcfg Character device for +.Nm +driver. +.Sh AUTHORS +Thomas Skibo +.Sh SEE ALSO +Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585) Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Sat Apr 27 22:47:52 2013 (r249998) +++ head/sys/arm/arm/cpufunc.c Sat Apr 27 23:07:49 2013 (r249999) @@ -1480,7 +1480,8 @@ set_cpufuncs() cputype == CPU_ID_CORTEXA8R2 || cputype == CPU_ID_CORTEXA8R3 || cputype == CPU_ID_CORTEXA9R1 || - cputype == CPU_ID_CORTEXA9R2) { + cputype == CPU_ID_CORTEXA9R2 || + cputype == CPU_ID_CORTEXA9R3) { cpufuncs = cortexa_cpufuncs; cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ get_cachetype_cp15(); Modified: head/sys/arm/arm/identcpu.c ============================================================================== --- head/sys/arm/arm/identcpu.c Sat Apr 27 22:47:52 2013 (r249998) +++ head/sys/arm/arm/identcpu.c Sat Apr 27 23:07:49 2013 (r249999) @@ -246,6 +246,8 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEXA, "Cortex A9-r2", generic_steppings }, + { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEXA, "Cortex A9-r3", + generic_steppings }, { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", sa110_steppings }, Modified: head/sys/arm/include/armreg.h ============================================================================== --- head/sys/arm/include/armreg.h Sat Apr 27 22:47:52 2013 (r249998) +++ head/sys/arm/include/armreg.h Sat Apr 27 23:07:49 2013 (r249999) @@ -152,6 +152,7 @@ #define CPU_ID_CORTEXA8R3 0x413fc080 #define CPU_ID_CORTEXA9R1 0x411fc090 #define CPU_ID_CORTEXA9R2 0x412fc090 +#define CPU_ID_CORTEXA9R3 0x413fc090 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 #define CPU_ID_TI925T 0x54029250 Modified: head/sys/dev/mmc/mmc.c ============================================================================== --- head/sys/dev/mmc/mmc.c Sat Apr 27 22:47:52 2013 (r249998) +++ head/sys/dev/mmc/mmc.c Sat Apr 27 23:07:49 2013 (r249999) @@ -1734,3 +1734,4 @@ DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); +DRIVER_MODULE(mmc, sdhci_fdt, mmc_driver, mmc_devclass, NULL, NULL); Modified: head/sys/dev/uart/uart.h ============================================================================== --- head/sys/dev/uart/uart.h Sat Apr 27 22:47:52 2013 (r249998) +++ head/sys/dev/uart/uart.h Sat Apr 27 23:07:49 2013 (r249999) @@ -72,6 +72,7 @@ extern struct uart_class uart_sbbc_class extern struct uart_class uart_z8530_class __attribute__((weak)); extern struct uart_class uart_lpc_class __attribute__((weak)); extern struct uart_class uart_pl011_class __attribute__((weak)); +extern struct uart_class uart_cdnc_class __attribute__((weak)); #ifdef PC98 struct uart_class *uart_pc98_getdev(u_long port); Modified: head/sys/dev/uart/uart_bus_fdt.c ============================================================================== --- head/sys/dev/uart/uart_bus_fdt.c Sat Apr 27 22:47:52 2013 (r249998) +++ head/sys/dev/uart/uart_bus_fdt.c Sat Apr 27 23:07:49 2013 (r249999) @@ -109,6 +109,8 @@ uart_fdt_probe(device_t dev) sc->sc_class = &uart_imx_class; else if (ofw_bus_is_compatible(dev, "arm,pl011")) sc->sc_class = &uart_pl011_class; + else if (ofw_bus_is_compatible(dev, "cadence,uart")) + sc->sc_class = &uart_cdnc_class; else return (ENXIO); @@ -196,6 +198,8 @@ uart_cpu_getdev(int devtype, struct uart class = &uart_ns8250_class; if (fdt_is_compatible(node, "arm,pl011")) class = &uart_pl011_class; + if (fdt_is_compatible(node, "cadence,uart")) + class = &uart_cdnc_class; di->bas.chan = 0; di->bas.regshft = (u_int)shift;