From owner-cvs-all@FreeBSD.ORG Wed Nov 2 21:21:54 2005 Return-Path: X-Original-To: cvs-all@freebsd.org Delivered-To: cvs-all@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 383CE16A41F; Wed, 2 Nov 2005 21:21:54 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from speedfactory.net (mail5.speedfactory.net [66.23.216.218]) by mx1.FreeBSD.org (Postfix) with ESMTP id 73D7943D49; Wed, 2 Nov 2005 21:21:53 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (unverified [66.23.211.162]) by speedfactory.net (SurgeMail 3.5b3) with ESMTP id 1259577 for multiple; Wed, 02 Nov 2005 16:19:52 -0500 Received: from localhost (john@localhost [127.0.0.1]) by server.baldwin.cx (8.13.1/8.13.1) with ESMTP id jA2LLmtW059571; Wed, 2 Nov 2005 16:21:49 -0500 (EST) (envelope-from jhb@freebsd.org) From: John Baldwin To: src-committers@freebsd.org Date: Wed, 2 Nov 2005 15:31:28 -0500 User-Agent: KMail/1.8.2 References: <200511022011.jA2KBlHQ005559@repoman.freebsd.org> In-Reply-To: <200511022011.jA2KBlHQ005559@repoman.freebsd.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-6" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200511021531.31837.jhb@freebsd.org> X-Spam-Status: No, score=-2.8 required=4.2 tests=ALL_TRUSTED autolearn=failed version=3.0.2 X-Spam-Checker-Version: SpamAssassin 3.0.2 (2004-11-16) on server.baldwin.cx X-Server: High Performance Mail Server - http://surgemail.com r=100 Cc: cvs-src@freebsd.org, cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/amd64/amd64 io_apic.c local_apic.c src/sys/amd64/include apicvar.h intr_machdep.h src/sys/i386/i386 io_apic.c local_apic.c src/sys/i386/include apicvar.h intr_machdep.h X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Nov 2005 21:21:54 -0000 On Wednesday 02 November 2005 03:11 pm, John Baldwin wrote: > jhb 2005-11-02 20:11:47 UTC > > FreeBSD src repository > > Modified files: > sys/amd64/amd64 io_apic.c local_apic.c > sys/amd64/include apicvar.h intr_machdep.h > sys/i386/i386 io_apic.c local_apic.c > sys/i386/include apicvar.h intr_machdep.h > Log: > Change the x86 code to allocate IDT vectors on-demand when an interrupt > source is first enabled similar to how intr_event's now allocate ithreads > on-demand. Previously, we would map IDT vectors 1:1 to IRQs. Since we > only have 191 available IDT vectors for I/O interrupts, this limited us > to only supporting IRQs 0-190 corresponding to the first 190 I/O APIC > intpins. On many machines, however, each PCI-X bus has its own APIC even > though it only has 1 or 2 devices, thus, we were reserving between 24 and > 32 IRQs just for 1 or 2 devices and thus 24 or 32 IDT vectors. With this > change, a machine with 100 IRQs but only 5 in use will only use up 5 IDT > vectors. Also, this change provides an API (apic_alloc_vector() and > apic_free_vector()) that will allow a future MSI interrupt source driver > to request IDT vectors for use by MSI interrupts on x86 machines. > > Tested on: amd64, i386 Forgot to mention that for now the algorithm is a very simple brain-dead one that just assigns each device interrupt the first free IDT vector and panics if all 191 are in use. -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org