From owner-freebsd-arm@freebsd.org Mon Feb 4 17:00:55 2019 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 03C4714D557B for ; Mon, 4 Feb 2019 17:00:55 +0000 (UTC) (envelope-from greg@unrelenting.technology) Received: from out.migadu.com (out.migadu.com [91.121.223.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "smtp.migadu.com", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C97A78EC02 for ; Mon, 4 Feb 2019 17:00:51 +0000 (UTC) (envelope-from greg@unrelenting.technology) Received: (Migadu outbound); Mon, 04 Feb 2019 17:00:44 +0000 Received: from [192.168.1.141] ([62.122.208.146]) by out.migadu.com (Haraka/2.8.16) with ESMTPSA id 2BD9F5A0-4E82-4C65-BB80-84A8433CDEC6.1 envelope-from (authenticated bits=0) (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 verify=FAIL); Mon, 04 Feb 2019 17:00:43 +0000 Date: Sun, 03 Feb 2019 20:36:24 +0300 From: Greg V Subject: Re: Scheduling on heterogeneous ARM SoC To: John F Carr Cc: freebsd-arm@freebsd.org Message-Id: <1549215384.4076.0@smtp.migadu.com> In-Reply-To: <34290296-577D-4A05-9FC8-1142A47909F5@exchange.mit.edu> References: <34290296-577D-4A05-9FC8-1142A47909F5@exchange.mit.edu> X-Mailer: geary/lite-gnome~g3766af013824-dirty MIME-Version: 1.0 Content-Type: text/plain; charset=windows-1251; format=flowed Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; bh=5SNhhP4SDrpnEDq6Q/CYzxkVLa65NYNfoYrVe2zaBuU=; c=relaxed/simple; d=unrelenting.technology; h=from:subject:date:to; s=default; b=Y0P3bgMPDXyrKknVwnsYWVmxFv5epPWPK7VW6Q6iElbnkr7U66nht+hgIbQQSH9a/O5uqQw4UEETfMIKui9+lnuLI7jTvWk2sQoTHawmKXN6boM0GK7dAfrYHQSvnJMrJE8/rLHsM8Yf3wlekXZ21suESF3MjwlpcfAq7hKrI4Y= X-Rspamd-Queue-Id: C97A78EC02 X-Spamd-Bar: ------ Authentication-Results: mx1.freebsd.org; dkim=pass header.d=unrelenting.technology header.s=default header.b=Y0P3bgMP; dmarc=pass (policy=none) header.from=unrelenting.technology; spf=pass (mx1.freebsd.org: domain of greg@unrelenting.technology designates 91.121.223.63 as permitted sender) smtp.mailfrom=greg@unrelenting.technology X-Spamd-Result: default: False [-6.66 / 15.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(-0.20)[unrelenting.technology:s=default]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(-0.20)[+ip4:91.121.223.63]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_THREE(0.00)[3]; TO_MATCH_ENVRCPT_SOME(0.00)[]; DKIM_TRACE(0.00)[unrelenting.technology:+]; RCPT_COUNT_TWO(0.00)[2]; DMARC_POLICY_ALLOW(-0.50)[unrelenting.technology,none]; MX_GOOD(-0.01)[aspmx1.migadu.com,aspmx2.migadu.com]; NEURAL_HAM_SHORT(-0.92)[-0.921,0]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; IP_SCORE(-2.73)[ip: (-9.89), ipnet: 91.121.0.0/16(-4.42), asn: 16276(0.68), country: FR(-0.02)]; ASN(0.00)[asn:16276, ipnet:91.121.0.0/16, country:FR]; RCVD_TLS_ALL(0.00)[] X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Feb 2019 17:00:55 -0000 On Sun, Feb 3, 2019 at 5:29 PM, John F Carr wrote: > Some ARM-based single board computers combine two types of Cortex=20 > processors, for example 4 A73 and 4 A 53 or 2 A72 and 4 A53. How=20 > does FreeBSD schedule processes on these chips? Does it use all=20 > cores at random, only the "big" or "little" set, or something more=20 > complicated? Pretty much "at random" i.e. doesn't take the differences between cores=20 into account. I'd really like to have a "fill up fastest cores first" mode, because=20 for building software on my RK3399 board I've had to either not do=20 anything and sometimes end up with big cores idling when little cores=20 are compiling, or to cpuset to big cores which would end up not=20 utilizing the little cores in highly parallel build phases=85 =