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From: "Rodney W. Grimes" <freebsd@pdx.rh.CN85.dnsmgr.net>
Message-Id: <201805221544.w4MFiuHn030796@pdx.rh.CN85.dnsmgr.net>
Subject: Re: svn commit: r334050 - head/sys/dev/cpuctl
In-Reply-To: <201805221538.w4MFcpkO072768@repo.freebsd.org>
To: Mark Johnston <markj@freebsd.org>
Date: Tue, 22 May 2018 08:44:56 -0700 (PDT)
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> Author: markj
> Date: Tue May 22 15:38:51 2018
> New Revision: 334050
> URL: https://svnweb.freebsd.org/changeset/base/334050
> 
> Log:
>   Flush caches before initiating a microcode update on Intel CPUs.
>   
>   This apparently works around issues with updates of certain Broadwell
>   CPUs.
>   
>   Reviewed by:	emaste, kib, sbruno
>   MFC after:	3 days
>   Differential Revision:	https://reviews.freebsd.org/D15520
> 
> Modified:
>   head/sys/dev/cpuctl/cpuctl.c
> 
> Modified: head/sys/dev/cpuctl/cpuctl.c
> ==============================================================================
> --- head/sys/dev/cpuctl/cpuctl.c	Tue May 22 15:35:38 2018	(r334049)
> +++ head/sys/dev/cpuctl/cpuctl.c	Tue May 22 15:38:51 2018	(r334050)
> @@ -367,8 +367,10 @@ update_intel(int cpu, cpuctl_update_args_t *args, stru
>  	rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */
>  
>  	/*
> -	 * Perform update.
> +	 * Perform update.  Flush caches first to work around seeingly

Did you mean seemingly?

> +	 * undocumented errata applying to some Broadwell CPUs.
>  	 */
> +	wbinvd();
>  	wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
>  	wrmsr_safe(MSR_BIOS_SIGN, 0);
>  
> 
> 

-- 
Rod Grimes                                                 rgrimes@freebsd.org