Date: Sun, 25 May 2003 15:51:16 -0700 (PDT) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 31873 for review Message-ID: <200305252251.h4PMpGuX015324@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=31873 Change 31873 by jmallett@jmallett_dalek on 2003/05/25 15:50:36 Use cpufunc-style mips_{rd,wr}_<coprocessor 0 register> stuff instead of NetBSD locore_mips3.S stuff which is about to mostly go away. I don't touch things related to configN on MIPS32/64 chips, as that's a can of worms I have absolutely ZERO desire to open. Affected files ... .. //depot/projects/mips/sys/mips/include/cpufunc.h#10 edit .. //depot/projects/mips/sys/mips/mips/cache.c#4 edit .. //depot/projects/mips/sys/mips/mips/cache_r5k.c#3 edit .. //depot/projects/mips/sys/mips/mips/machdep.c#28 edit .. //depot/projects/mips/sys/mips/sgimips/ip22.c#3 edit Differences ... ==== //depot/projects/mips/sys/mips/include/cpufunc.h#10 (text+ko) ==== @@ -33,21 +33,51 @@ #include <sys/types.h> #include <machine/cpuregs.h> -uint32_t mips_cp0_cause_read(void); -void mips_cp0_cause_write(uint32_t); -uint32_t mips_cp0_status_read(void); -void mips_cp0_status_write(uint32_t); +static __inline void +mips_wbflush(void) +{ + __asm __volatile ("sync" : : : "memory"); +} + +#define MIPS_RDRW32_COP0(n,r) \ +static __inline u_int32_t \ +mips_rd_ ## n (void) \ +{ \ + int v0; \ + __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ + : [v0] "=&r"(v0)); \ + return (v0); \ +} \ +static __inline void \ +mips_wr_ ## n (u_int32_t a0) \ +{ \ + __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ + __XSTRING(COP0_SYNC)";" \ + "nop;" \ + "nop;" \ + : \ + : [a0] "r"(a0)); \ +} + +MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE) +MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG) +MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT) +MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED) +MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE) +MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS) static __inline register_t intr_disable(void) { register_t s; - mips_cp0_status_write((s = mips_cp0_status_read()) & ~MIPS_SR_IE); + s = mips_rd_status(); + mips_wr_status(s & ~MIPS_SR_IE); + return (s); } -#define intr_restore(s) mips_cp0_status_write((s)) +#define intr_restore(s) mips_wr_status((s)) static __inline void mips_break(void) @@ -64,7 +94,7 @@ static __inline void mips_write_membar(void) { - __asm __volatile ("sync" : : : "memory"); + mips_wbflush(); } #endif /* _KERNEL */ ==== //depot/projects/mips/sys/mips/mips/cache.c#4 (text+ko) ==== @@ -561,7 +561,9 @@ mips3_get_cache_config(int csizebase) { int has_sdcache_enable = 0; - uint32_t config = mips3_cp0_config_read(); + uint32_t config; + + config = mips_rd_config(); mips_picache_size = MIPS3_CONFIG_CACHE_SIZE(config, MIPS3_CONFIG_IC_MASK, csizebase, MIPS3_CONFIG_IC_SHIFT); @@ -617,7 +619,7 @@ /* MIPS32/MIPS64, use coprocessor 0 config registers */ uint32_t cfg, cfg1; - cfg = mips3_cp0_config_read(); + cfg = mips_rd_config(); cfg1 = mipsNN_cp0_config1_read(); #ifdef MIPS_DISABLE_L1_CACHE ==== //depot/projects/mips/sys/mips/mips/cache_r5k.c#3 (text+ko) ==== @@ -227,9 +227,9 @@ return; } - ostatus = mips_cp0_status_read(); + ostatus = mips_rd_status(); - mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); + mips_wr_status(ostatus & ~MIPS_SR_INT_IE); while (va < eva) { __asm __volatile("nop; nop; nop; nop;"); @@ -237,7 +237,7 @@ va += 32; } - mips_cp0_status_write(ostatus); + mips_wr_status(ostatus); } void @@ -248,9 +248,9 @@ va = trunc_line(va); - ostatus = mips_cp0_status_read(); + ostatus = mips_rd_status(); - mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); + mips_wr_status(ostatus & ~MIPS_SR_INT_IE); while ((eva - va) >= (32 * 32)) { (void) *(__volatile int *)MIPS_PHYS_TO_KSEG1(0); @@ -265,7 +265,7 @@ va += 32; } - mips_cp0_status_write(ostatus); + mips_wr_status(ostatus); } void @@ -406,9 +406,9 @@ va = trunc_line(va); - ostatus = mips_cp0_status_read(); + ostatus = mips_rd_status(); - mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); + mips_wr_status(ostatus & ~MIPS_SR_INT_IE); while (va < eva) { __asm __volatile("nop; nop; nop; nop;"); @@ -416,7 +416,7 @@ va += 32; } - mips_cp0_status_write(ostatus); + mips_wr_status(ostatus); } void @@ -427,9 +427,9 @@ va = trunc_line(va); - ostatus = mips_cp0_status_read(); + ostatus = mips_rd_status(); - mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); + mips_wr_status(ostatus & ~MIPS_SR_INT_IE); /* * Between blasts of big cache chunks, give interrupts @@ -447,7 +447,7 @@ va += 32; } - mips_cp0_status_write(ostatus); + mips_wr_status(ostatus); } void @@ -500,9 +500,9 @@ va = trunc_line(va); - ostatus = mips_cp0_status_read(); + ostatus = mips_rd_status(); - mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); + mips_wr_status(ostatus & ~MIPS_SR_INT_IE); while (va < eva) { __asm __volatile("nop; nop; nop; nop;"); @@ -510,7 +510,7 @@ va += 32; } - mips_cp0_status_write(ostatus); + mips_wr_status(ostatus); } void @@ -521,9 +521,9 @@ va = trunc_line(va); - ostatus = mips_cp0_status_read(); + ostatus = mips_rd_status(); - mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); + mips_wr_status(ostatus & ~MIPS_SR_INT_IE); /* * Between blasts of big cache chunks, give interrupts @@ -541,7 +541,7 @@ va += 32; } - mips_cp0_status_write(ostatus); + mips_wr_status(ostatus); } void ==== //depot/projects/mips/sys/mips/mips/machdep.c#28 (text+ko) ==== @@ -579,7 +579,7 @@ mips64_TBIAP, mips64_TBIS, mips64_TLBUpdate, - mips64_wbflush, + mips_wbflush, }; static void @@ -633,7 +633,7 @@ mips_dcache_wbinv_all(); /* Clear BEV in SR so we start handling our own exceptions */ - mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); + mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV); } /* @@ -686,7 +686,7 @@ /* MIPS32/MIPS64, use coprocessor 0 config registers */ uint32_t cfg, cfg1; - cfg = mips3_cp0_config_read(); + cfg = mips_rd_config(); cfg1 = mipsNN_cp0_config1_read(); /* pick CPU type */ @@ -757,9 +757,9 @@ switch (cpu_arch) { case CPU_ARCH_MIPS3: case CPU_ARCH_MIPS64: - mips3_cp0_wired_write(0); + mips_wr_wired(0); mips64_TBIA(mips_num_tlb_entries); - mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES); + mips_wr_wired(MIPS3_TLB_WIRED_UPAGES); mips64_vector_init(); memcpy(mips_locoresw, mips64_locoresw, sizeof(mips_locoresw)); break; ==== //depot/projects/mips/sys/mips/sgimips/ip22.c#3 (text+ko) ==== @@ -215,11 +215,11 @@ *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fa00014) = 0; if (ipending & MIPS_INT_MASK_5) { - last_clk_intr = mips3_cp0_count_read(); + last_clk_intr = mips_rd_count(); next_clk_intr += curcpu()->ci_cycles_per_hz; - mips3_cp0_compare_write(next_clk_intr); - newcnt = mips3_cp0_count_read(); + mips_wr_compare(next_clk_intr); + newcnt = mips_rd_count(); /* * Missed one or more clock interrupts, so let's start @@ -229,7 +229,7 @@ missed_clk_intrs++; next_clk_intr = newcnt + curcpu()->ci_cycles_per_hz; - mips3_cp0_compare_write(next_clk_intr); + mips_wr_compare(next_clk_intr); } cf.pc = pc; @@ -432,7 +432,7 @@ { uint32_t res, count; - count = mips3_cp0_count_read() - last_clk_intr; + count = mips_rd_count() - last_clk_intr; MIPS_COUNT_TO_MHZ(curcpu(), count, res); return (res); } @@ -461,7 +461,7 @@ *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(tcount) = sampletime & 0xff; *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(tcount) = sampletime >> 8; - startctr = mips3_cp0_count_read(); + startctr = mips_rd_count(); /* Wait for the MSB to count down to zero */ do { @@ -469,7 +469,7 @@ lsb = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(tcount) & 0xff; msb = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(tcount) & 0xff; - endctr = mips3_cp0_count_read(); + endctr = mips_rd_count(); } while (msb); /* Turn off timer */
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