From owner-svn-src-all@freebsd.org Tue Dec 6 13:55:20 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C9715C63F5D; Tue, 6 Dec 2016 13:55:20 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8A4CC1B2A; Tue, 6 Dec 2016 13:55:20 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uB6DtJGn097968; Tue, 6 Dec 2016 13:55:19 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uB6DtJLW097963; Tue, 6 Dec 2016 13:55:19 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201612061355.uB6DtJLW097963@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 6 Dec 2016 13:55:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r309618 - in head/sys: arm/arm arm64/arm64 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Dec 2016 13:55:20 -0000 Author: andrew Date: Tue Dec 6 13:55:19 2016 New Revision: 309618 URL: https://svnweb.freebsd.org/changeset/base/309618 Log: Move the common bit manipulation macros from the GICv3 header to the common GIC header file. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Modified: head/sys/arm/arm/gic.c head/sys/arm/arm/gic_common.h head/sys/arm64/arm64/gic_v3.c head/sys/arm64/arm64/gic_v3_reg.h head/sys/arm64/arm64/gicv3_its.c Modified: head/sys/arm/arm/gic.c ============================================================================== --- head/sys/arm/arm/gic.c Tue Dec 6 13:46:12 2016 (r309617) +++ head/sys/arm/arm/gic.c Tue Dec 6 13:55:19 2016 (r309618) @@ -171,14 +171,14 @@ static inline void gic_irq_unmask(struct arm_gic_softc *sc, u_int irq) { - gic_d_write_4(sc, GICD_ISENABLER(irq), (1UL << (irq & 0x1F))); + gic_d_write_4(sc, GICD_ISENABLER(irq), GICD_I_MASK(irq)); } static inline void gic_irq_mask(struct arm_gic_softc *sc, u_int irq) { - gic_d_write_4(sc, GICD_ICENABLER(irq), (1UL << (irq & 0x1F))); + gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq)); } #endif @@ -274,9 +274,9 @@ arm_gic_init_secondary(device_t dev) /* * Activate the timer interrupts: virtual, secure, and non-secure. */ - gic_d_write_4(sc, GICD_ISENABLER(27), (1UL << (27 & 0x1F))); - gic_d_write_4(sc, GICD_ISENABLER(29), (1UL << (29 & 0x1F))); - gic_d_write_4(sc, GICD_ISENABLER(30), (1UL << (30 & 0x1F))); + gic_d_write_4(sc, GICD_ISENABLER(27), GICD_I_MASK(27)); + gic_d_write_4(sc, GICD_ISENABLER(29), GICD_I_MASK(29)); + gic_d_write_4(sc, GICD_ISENABLER(30), GICD_I_MASK(30)); } #endif /* INTRNG */ #endif /* SMP */ @@ -447,7 +447,7 @@ arm_gic_attach(device_t dev) /* Get the number of interrupts */ sc->typer = gic_d_read_4(sc, GICD_TYPER); - nirqs = 32 * ((sc->typer & 0x1f) + 1); + nirqs = GICD_TYPER_I_NUM(sc->typer); #ifdef INTRNG if (arm_gic_register_isrcs(sc, nirqs)) { Modified: head/sys/arm/arm/gic_common.h ============================================================================== --- head/sys/arm/arm/gic_common.h Tue Dec 6 13:46:12 2016 (r309617) +++ head/sys/arm/arm/gic_common.h Tue Dec 6 13:55:19 2016 (r309618) @@ -35,6 +35,7 @@ /* Common register values */ #define GICD_CTLR 0x0000 /* v1 ICDDCR */ #define GICD_TYPER 0x0004 /* v1 ICDICTR */ +#define GICD_TYPER_I_NUM(n) ((((n) & 0x1F) + 1) * 32) #define GICD_IIDR 0x0008 /* v1 ICDIIDR */ #define GICD_IIDR_PROD_SHIFT 24 #define GICD_IIDR_PROD_MASK 0xff000000 @@ -54,13 +55,17 @@ (((x) & GICD_IIDR_IMPL_MASK) >> GICD_IIDR_IMPL_SHIFT) #define GICD_IGROUPR(n) (0x0080 + (((n) >> 5) * 4)) /* v1 ICDISER */ #define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) /* v1 ICDISER */ +#define GICD_I_MASK(n) (1ul << ((n) & 0x1f)) +#define GICD_I_PER_ISENABLERn 32 #define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4)) /* v1 ICDICER */ #define GICD_ISPENDR(n) (0x0200 + (((n) >> 5) * 4)) /* v1 ICDISPR */ #define GICD_ICPENDR(n) (0x0280 + (((n) >> 5) * 4)) /* v1 ICDICPR */ #define GICD_ICACTIVER(n) (0x0380 + (((n) >> 5) * 4)) /* v1 ICDABR */ #define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) /* v1 ICDIPR */ +#define GICD_I_PER_IPRIORITYn 4 #define GICD_ITARGETSR(n) (0x0800 + (((n) >> 2) * 4)) /* v1 ICDIPTR */ #define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4)) /* v1 ICDICFR */ +#define GICD_I_PER_ICFGRn 16 /* First bit is a polarity bit (0 - low, 1 - high) */ #define GICD_ICFGR_POL_LOW (0 << 0) #define GICD_ICFGR_POL_HIGH (1 << 0) Modified: head/sys/arm64/arm64/gic_v3.c ============================================================================== --- head/sys/arm64/arm64/gic_v3.c Tue Dec 6 13:46:12 2016 (r309617) +++ head/sys/arm64/arm64/gic_v3.c Tue Dec 6 13:55:19 2016 (r309618) @@ -65,6 +65,7 @@ __FBSDID("$FreeBSD$"); #include "pic_if.h" +#include #include "gic_v3_reg.h" #include "gic_v3_var.h" Modified: head/sys/arm64/arm64/gic_v3_reg.h ============================================================================== --- head/sys/arm64/arm64/gic_v3_reg.h Tue Dec 6 13:46:12 2016 (r309617) +++ head/sys/arm64/arm64/gic_v3_reg.h Tue Dec 6 13:55:19 2016 (r309618) @@ -59,36 +59,13 @@ /* * Registers (v2/v3) */ -#define GICD_CTLR (0x0000) -#define GICD_CTLR_G1 (1 << 0) -#define GICD_CTLR_G1A (1 << 1) -#define GICD_CTLR_ARE_NS (1 << 4) -#define GICD_CTLR_RWP (1 << 31) - -#define GICD_TYPER (0x0004) -#define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) -#define GICD_TYPER_I_NUM(n) ((((n) & 0x1F) + 1) * 32) - -#define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) -#define GICD_I_PER_ISENABLERn (32) - -#define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4)) -#define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) -#define GICD_I_PER_IPRIORITYn (4) - -#define GICD_I_MASK(n) (1 << ((n) % 32)) - -#define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4)) -/* First bit is a polarity bit (0 - low, 1 - high) */ -#define GICD_ICFGR_POL_LOW (0 << 0) -#define GICD_ICFGR_POL_HIGH (1 << 0) -#define GICD_ICFGR_POL_MASK (0x1) -/* Second bit is a trigger bit (0 - level, 1 - edge) */ -#define GICD_ICFGR_TRIG_LVL (0 << 1) -#define GICD_ICFGR_TRIG_EDGE (1 << 1) -#define GICD_ICFGR_TRIG_MASK (0x2) - -#define GICD_I_PER_ICFGRn (16) +/* GICD_CTLR */ +#define GICD_CTLR_G1 (1 << 0) +#define GICD_CTLR_G1A (1 << 1) +#define GICD_CTLR_ARE_NS (1 << 4) +#define GICD_CTLR_RWP (1 << 31) +/* GICD_TYPER */ +#define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) /* * Registers (v3) Modified: head/sys/arm64/arm64/gicv3_its.c ============================================================================== --- head/sys/arm64/arm64/gicv3_its.c Tue Dec 6 13:46:12 2016 (r309617) +++ head/sys/arm64/arm64/gicv3_its.c Tue Dec 6 13:55:19 2016 (r309618) @@ -55,6 +55,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include