From owner-svn-src-head@FreeBSD.ORG Thu Aug 29 16:26:04 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id EF09FA94; Thu, 29 Aug 2013 16:26:04 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id DC73425CE; Thu, 29 Aug 2013 16:26:04 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r7TGQ4d3036067; Thu, 29 Aug 2013 16:26:04 GMT (envelope-from marcel@svn.freebsd.org) Received: (from marcel@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r7TGQ4RY036066; Thu, 29 Aug 2013 16:26:04 GMT (envelope-from marcel@svn.freebsd.org) Message-Id: <201308291626.r7TGQ4RY036066@svn.freebsd.org> From: Marcel Moolenaar Date: Thu, 29 Aug 2013 16:26:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r255031 - head/sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Aug 2013 16:26:05 -0000 Author: marcel Date: Thu Aug 29 16:26:04 2013 New Revision: 255031 URL: http://svnweb.freebsd.org/changeset/base/255031 Log: Work-around a timing problem with the ITE IT8513E now that the core calls ns8250_bus_ipend() almost immediately after ns8250_bus_attach(). As it appears, a line break condition is being signalled for almost all received characters due to this. A delay of 150ms seems enough to allow the H/W to settle and to avoid the problem. More analysis is needed, but for now a regression has been addressed. Reported by: kevlo@ Tested by: kevlo@ Modified: head/sys/dev/uart/uart_dev_ns8250.c Modified: head/sys/dev/uart/uart_dev_ns8250.c ============================================================================== --- head/sys/dev/uart/uart_dev_ns8250.c Thu Aug 29 15:59:05 2013 (r255030) +++ head/sys/dev/uart/uart_dev_ns8250.c Thu Aug 29 16:26:04 2013 (r255031) @@ -453,7 +453,19 @@ ns8250_bus_attach(struct uart_softc *sc) ns8250->ier |= ns8250->ier_rxbits; uart_setreg(bas, REG_IER, ns8250->ier); uart_barrier(bas); - + + /* + * Timing of the H/W access was changed with r253161 of uart_core.c + * It has been observed that an ITE IT8513E would signal a break + * condition with pretty much every character it received, unless + * it had enough time to settle between ns8250_bus_attach() and + * ns8250_bus_ipend() -- which it accidentally had before r253161. + * It's not understood why the UART chip behaves this way and it + * could very well be that the DELAY make the H/W work in the same + * accidental manner as before. More analysis is warranted, but + * at least now we fixed a known regression. + */ + DELAY(150); return (0); }