Date: Wed, 12 Aug 2015 17:09:58 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r286675 - head/sys/arm64/include Message-ID: <201508121709.t7CH9wP2033865@repo.freebsd.org>
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Author: andrew Date: Wed Aug 12 17:09:57 2015 New Revision: 286675 URL: https://svnweb.freebsd.org/changeset/base/286675 Log: Add the CNTHCTL_EL2 register bits missed in r286674 Modified: head/sys/arm64/include/armreg.h Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Wed Aug 12 17:06:22 2015 (r286674) +++ head/sys/arm64/include/armreg.h Wed Aug 12 17:09:57 2015 (r286675) @@ -41,6 +41,13 @@ #define WRITE_SPECIALREG(reg, val) \ __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) +/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ +#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ +#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ +#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ +#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ +#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ + /* CPACR_EL1 */ #define CPACR_FPEN_MASK (0x3 << 20) #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
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