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Date:      Wed, 27 Feb 2019 14:20:28 +0000 (UTC)
From:      Emmanuel Vadot <manu@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r344623 - head/sys/arm64/rockchip/clk
Message-ID:  <201902271420.x1REKSS0008710@repo.freebsd.org>

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Author: manu
Date: Wed Feb 27 14:20:28 2019
New Revision: 344623
URL: https://svnweb.freebsd.org/changeset/base/344623

Log:
  arm64: rockchip: clk_pll: Multiple improvement
  
  Remove the mode_val from the clock definition as it's a bit unreadable.
  Use mode_shift to represent which bit control the mode in the register.
  Simplify some case where we can avoid a register read before changing it.
  Set the PLL back to normal mode after the PLL have stabilized.
  
  Discussed with:	 mmel
  MFC after:	1 week

Modified:
  head/sys/arm64/rockchip/clk/rk3328_cru.c
  head/sys/arm64/rockchip/clk/rk_clk_pll.c
  head/sys/arm64/rockchip/clk/rk_clk_pll.h

Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk3328_cru.c	Wed Feb 27 14:01:13 2019	(r344622)
+++ head/sys/arm64/rockchip/clk/rk3328_cru.c	Wed Feb 27 14:20:28 2019	(r344623)
@@ -523,7 +523,7 @@ static struct rk_clk_pll_def apll = {
 	.gate_offset = 0x200,
 	.gate_shift = 0,
 	.mode_reg = 0x80,
-	.mode_val = 0x1,
+	.mode_shift = 1,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.frac_rates = rk3328_pll_frac_rates,
 };
@@ -539,7 +539,7 @@ static struct rk_clk_pll_def dpll = {
 	.gate_offset = 0x200,
 	.gate_shift = 1,
 	.mode_reg = 0x80,
-	.mode_val = 0x8,
+	.mode_shift = 4,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 };
 
@@ -552,7 +552,7 @@ static struct rk_clk_pll_def cpll = {
 	},
 	.base_offset = 0x40,
 	.mode_reg = 0x80,
-	.mode_val = 0x80,
+	.mode_shift = 8,
 	.rates = rk3328_pll_rates,
 };
 
@@ -567,7 +567,7 @@ static struct rk_clk_pll_def gpll = {
 	.gate_offset = 0x200,
 	.gate_shift = 2,
 	.mode_reg = 0x80,
-	.mode_val = 0x800,
+	.mode_shift = 12,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.frac_rates = rk3328_pll_frac_rates,
 };
@@ -583,7 +583,7 @@ static struct rk_clk_pll_def npll = {
 	.gate_offset = 0x200,
 	.gate_shift = 12,
 	.mode_reg = 0x80,
-	.mode_val = 0x2,
+	.mode_shift = 1,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.rates = rk3328_pll_rates,
 };

Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk_clk_pll.c	Wed Feb 27 14:01:13 2019	(r344622)
+++ head/sys/arm64/rockchip/clk/rk_clk_pll.c	Wed Feb 27 14:20:28 2019	(r344623)
@@ -48,7 +48,7 @@ struct rk_clk_pll_sc {
 	uint32_t	gate_shift;
 
 	uint32_t	mode_reg;
-	uint32_t	mode_val;
+	uint32_t	mode_shift;
 
 	uint32_t	flags;
 
@@ -120,6 +120,10 @@ rk_clk_pll_set_gate(struct clknode *clk, bool enable)
 
 #define	RK3328_CLK_PLL_LOCK_MASK	0x400
 
+#define	RK3328_CLK_PLL_MODE_SLOW	0
+#define	RK3328_CLK_PLL_MODE_NORMAL	1
+#define	RK3328_CLK_PLL_MODE_MASK	0x1
+
 static int
 rk3328_clk_pll_init(struct clknode *clk, device_t dev)
 {
@@ -207,7 +211,8 @@ rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t 
 	DEVICE_LOCK(clk);
 
 	/* Setting to slow mode during frequency change */
-	reg = sc->mode_val << 16;
+	reg = (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) <<
+		RK_CLK_PLL_MASK_SHIFT;
 	dprintf("Set PLL_MODEREG to %x\n", reg);
 	WRITE4(clk, sc->mode_reg, reg);
 
@@ -219,13 +224,12 @@ rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t 
 	WRITE4(clk, sc->base_offset, reg);
 
 	/* Setting dsmpd, postdiv2 and refdiv */
-	READ4(clk, sc->base_offset + 0x4, &reg);
-	reg &= ~(RK3328_CLK_PLL_DSMPD_MASK | RK3328_CLK_PLL_POSTDIV2_MASK |
-	    RK3328_CLK_PLL_REFDIV_MASK);
 	reg = (rates->dsmpd << RK3328_CLK_PLL_DSMPD_SHIFT) |
 		(rates->postdiv2 << RK3328_CLK_PLL_POSTDIV2_SHIFT) |
 		(rates->refdiv << RK3328_CLK_PLL_REFDIV_SHIFT);
-	reg |= (RK3328_CLK_PLL_DSMPD_MASK | RK3328_CLK_PLL_POSTDIV2_MASK | RK3328_CLK_PLL_REFDIV_MASK) << 16;
+	reg |= (RK3328_CLK_PLL_DSMPD_MASK |
+	    RK3328_CLK_PLL_POSTDIV2_MASK |
+	    RK3328_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT;
 	dprintf("Set PLL_CON1 to %x\n", reg);
 	WRITE4(clk, sc->base_offset + 0x4, reg);
 
@@ -236,11 +240,6 @@ rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t 
 	dprintf("Set PLL_CON2 to %x\n", reg);
 	WRITE4(clk, sc->base_offset + 0x8, reg);
 
-	/* Setting to normal mode */
-	reg = sc->mode_val << 16 | sc->mode_val;
-	dprintf("Set PLL_MODEREG to %x\n", reg);
-	WRITE4(clk, sc->mode_reg, reg);
-
 	/* Reading lock */
 	for (timeout = 1000; timeout; timeout--) {
 		READ4(clk, sc->base_offset + 0x4, &reg);
@@ -249,6 +248,13 @@ rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t 
 		DELAY(1);
 	}
 
+	/* Set back to normal mode */
+	reg = (RK3328_CLK_PLL_MODE_NORMAL << sc->mode_shift);
+	reg |= (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) <<
+		RK_CLK_PLL_MASK_SHIFT;
+	dprintf("Set PLL_MODEREG to %x\n", reg);
+	WRITE4(clk, sc->mode_reg, reg);
+
 	DEVICE_UNLOCK(clk);
 
 	*stop = 1;
@@ -284,7 +290,7 @@ rk3328_clk_pll_register(struct clkdom *clkdom, struct 
 	sc->gate_offset = clkdef->gate_offset;
 	sc->gate_shift = clkdef->gate_shift;
 	sc->mode_reg = clkdef->mode_reg;
-	sc->mode_val = clkdef->mode_val;
+	sc->mode_shift = clkdef->mode_shift;
 	sc->flags = clkdef->flags;
 	sc->rates = clkdef->rates;
 	sc->frac_rates = clkdef->frac_rates;
@@ -339,9 +345,8 @@ rk3399_clk_pll_init(struct clknode *clk, device_t dev)
 	sc = clknode_get_softc(clk);
 
 	/* Setting to normal mode */
-	READ4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET, &reg);
-	reg &= ~RK3399_CLK_PLL_MODE_MASK;
-	reg |= RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
+	reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
+	reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
 	WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET,
 	    reg | RK3399_CLK_PLL_WRITE_MASK);
 
@@ -424,25 +429,23 @@ rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t 
 
 	DEVICE_LOCK(clk);
 
-	/* Setting to slow mode during frequency change */
+	/* Set to slow mode during frequency change */
 	reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT;
 	reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
 	WRITE4(clk, sc->base_offset + 0xC, reg);
 
 	/* Setting fbdiv */
-	READ4(clk, sc->base_offset, &reg);
-	reg &= ~RK3399_CLK_PLL_FBDIV_MASK;
-	reg |= rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT;
-	WRITE4(clk, sc->base_offset, reg | RK3399_CLK_PLL_WRITE_MASK);
+	reg = rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT;
+	reg |= RK3399_CLK_PLL_FBDIV_MASK << RK_CLK_PLL_MASK_SHIFT;
+	WRITE4(clk, sc->base_offset, reg);
 
 	/* Setting postdiv1, postdiv2 and refdiv */
-	READ4(clk, sc->base_offset + 0x4, &reg);
-	reg &= ~(RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK |
-	    RK3399_CLK_PLL_REFDIV_MASK);
-	reg |= rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT;
+	reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT;
 	reg |= rates->postdiv2 << RK3399_CLK_PLL_POSTDIV2_SHIFT;
 	reg |= rates->refdiv << RK3399_CLK_PLL_REFDIV_SHIFT;
-	WRITE4(clk, sc->base_offset + 0x4, reg | RK3399_CLK_PLL_WRITE_MASK);
+	reg |= (RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK |
+	    RK3399_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT;
+	WRITE4(clk, sc->base_offset + 0x4, reg);
 
 	/* Setting frac */
 	READ4(clk, sc->base_offset + 0x8, &reg);
@@ -450,12 +453,10 @@ rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t 
 	reg |= rates->frac << RK3399_CLK_PLL_FRAC_SHIFT;
 	WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK);
 
-	/* Setting to normal mode and dsmpd */
-	READ4(clk, sc->base_offset + 0xC, &reg);
-	reg &= ~RK3399_CLK_PLL_MODE_MASK;
-	reg |= RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
-	reg |= rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT;
-	WRITE4(clk, sc->base_offset + 0xC, reg | RK3399_CLK_PLL_WRITE_MASK);
+	/* Set dsmpd */
+	reg = rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT;
+	reg |= RK3399_CLK_PLL_DSMPD_MASK << RK_CLK_PLL_MASK_SHIFT;
+	WRITE4(clk, sc->base_offset + 0xC, reg);
 
 	/* Reading lock */
 	for (timeout = 1000; timeout; timeout--) {
@@ -465,6 +466,11 @@ rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t 
 		DELAY(1);
 	}
 
+	/* Set back to normal mode */
+	reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
+	reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
+	WRITE4(clk, sc->base_offset + 0xC, reg);
+
 	DEVICE_UNLOCK(clk);
 
 	*stop = 1;
@@ -499,8 +505,6 @@ rk3399_clk_pll_register(struct clkdom *clkdom, struct 
 	sc->base_offset = clkdef->base_offset;
 	sc->gate_offset = clkdef->gate_offset;
 	sc->gate_shift = clkdef->gate_shift;
-	sc->mode_reg = clkdef->mode_reg;
-	sc->mode_val = clkdef->mode_val;
 	sc->flags = clkdef->flags;
 	sc->rates = clkdef->rates;
 	sc->frac_rates = clkdef->frac_rates;

Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.h
==============================================================================
--- head/sys/arm64/rockchip/clk/rk_clk_pll.h	Wed Feb 27 14:01:13 2019	(r344622)
+++ head/sys/arm64/rockchip/clk/rk_clk_pll.h	Wed Feb 27 14:20:28 2019	(r344623)
@@ -51,7 +51,7 @@ struct rk_clk_pll_def {
 	uint32_t		gate_shift;
 
 	uint32_t		mode_reg;
-	uint32_t		mode_val;
+	uint32_t		mode_shift;
 
 	uint32_t		flags;

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