From owner-freebsd-arch Wed Jan 2 16:29:40 2002 Delivered-To: freebsd-arch@freebsd.org Received: from srv1.cosmo-project.de (srv1.cosmo-project.de [213.83.6.106]) by hub.freebsd.org (Postfix) with ESMTP id F1AD837B41E; Wed, 2 Jan 2002 16:29:36 -0800 (PST) Received: (from uucp@localhost) by srv1.cosmo-project.de (8.11.6/8.11.6) with UUCP id g030TQO05744; Thu, 3 Jan 2002 01:29:27 +0100 (CET) (envelope-from ticso@cicely9.cicely.de) Received: from mail.cicely.de (cicely20.cicely.de [10.1.1.22]) by cicely5.cicely.de (8.12.1/8.12.1) with ESMTP id g030PNtx046147; Thu, 3 Jan 2002 01:25:24 +0100 (CET)?g (envelope-from ticso@cicely9.cicely.de) Received: from cicely9.cicely.de (cicely9.cicely.de [10.1.7.11]) by mail.cicely.de (8.11.0/8.11.0) with ESMTP id g030PNW12902; Thu, 3 Jan 2002 01:25:23 +0100 (CET) Received: (from ticso@localhost) by cicely9.cicely.de (8.11.6/8.11.6) id g030PM162274; Thu, 3 Jan 2002 01:25:22 +0100 (CET) (envelope-from ticso) Date: Thu, 3 Jan 2002 01:25:22 +0100 From: Bernd Walter To: Michal Mertl , Matthew Dillon , Bruce Evans , Mike Smith , Bernd Walter , arch@FreeBSD.ORG Subject: Re: When to use atomic_ functions? (was: 64 bit counters) Message-ID: <20020103002521.GB53199@cicely9.cicely.de> References: <200201012349.g01NnKA40071@apollo.backplane.com> <20020103095701.B561@gsmx07.alcatel.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20020103095701.B561@gsmx07.alcatel.com.au> User-Agent: Mutt/1.3.24i X-Operating-System: FreeBSD cicely9.cicely.de 5.0-CURRENT alpha Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG On Thu, Jan 03, 2002 at 09:57:02AM +1100, Peter Jeremy wrote: > On 2002-Jan-02 15:53:55 +0100, Michal Mertl wrote: > >I don't know how much time will be wasted - my measurements on pII show > >the atomic_ operations aren't that expensive. > > As Matt has pointed out, this is only true if you have a single > processor. Atomic operations always translate into bus cycles - and > the bus is roughly an order of magnitude slower than the CPU core for > current CPUs. The worst situation is where a common counter is > updated by a random CPU - the counter will virtually always be in > another CPU's cache, requiring multiple bus cycles to transfer the > data. > > Also, many RISC processors (eg Alpha) don't have locked read-modify- > write primitives. On the Alpha, you need an instruction sequence: > loop: load_locked memory->register > update register > store_conditional register->memory > if not success goto loop > with a few memory barriers added to ensure that the load/store are > visible to other CPUs. The store_conditional will fail if your CPU > was interrupted or if another CPU updated an implementation-defined > region including the specified memory address. (64-bit atomic > operations on the IA32 use the same approach - using CMPXCHG8B as the > store_conditional instruction). My Alpha Architecture Handbook says that the barrier is unneeded. I have no clue why they are there. -- B.Walter COSMO-Project http://www.cosmo-project.de ticso@cicely.de Usergroup info@cosmo-project.de To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message