Date: Sat, 27 Apr 2013 23:59:15 +0000 (UTC) From: "Wojciech A. Koszek" <wkoszek@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r250001 - head/share/man/man4/man4.arm Message-ID: <201304272359.r3RNxFQM025029@svn.freebsd.org>
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Author: wkoszek Date: Sat Apr 27 23:59:15 2013 New Revision: 250001 URL: http://svnweb.freebsd.org/changeset/base/250001 Log: Polish devcfg(4) slightly: add \n after the end of every sentence. Modified: head/share/man/man4/man4.arm/devcfg.4 Modified: head/share/man/man4/man4.arm/devcfg.4 ============================================================================== --- head/share/man/man4/man4.arm/devcfg.4 Sat Apr 27 23:36:01 2013 (r250000) +++ head/share/man/man4/man4.arm/devcfg.4 Sat Apr 27 23:59:15 2013 (r250001) @@ -39,19 +39,20 @@ can be used to configure the PL (FPGA) s .Pp On the first write to the character device at file offset 0, the devcfg driver asserts the top-level PL reset signals, disables the PS-PL level shifters, -and clears the PL configuration. Write data is sent to -the PCAP (processor configuration access port). When the PL asserts the -DONE signal, the devcfg driver will enable the level shifters and release -the top-level PL reset signals. +and clears the PL configuration. +Write data is sent to the PCAP (processor configuration access port). +When the PL asserts the DONE signal, the devcfg driver will enable the level +shifters and release the top-level PL reset signals. .Pp -The PL (FPGA) can be configured by writing the bitstream to the -character device like this: +The PL (FPGA) can be configured by writing the bitstream to the character +device like this: .Bd -literal -offset indent cat design.bit.bin > /dev/devcfg .Ed .Pp The file should not be confused with the .bit file output by the FPGA -design tools. It is the binary form of the configuration bitstream. +design tools. +It is the binary form of the configuration bitstream. The Xilinx .Pa promgen tool can do the conversion: @@ -65,15 +66,17 @@ variables: .Bl -tag -width 12 .It Va hw.fpga.pl_done .Pp -This variable always reflects the status of the PL's DONE signal. A 1 -means the PL section has been properly programmed. +This variable always reflects the status of the PL's DONE signal. +A 1 means the PL section has been properly programmed. .It Va hw.fpga.en_level_shifters .Pp This variable controls if the PS-PL level shifters are enabled after the -PL section has been reconfigured. This variable is 1 by default but setting -it to 0 allows the PL section to be programmed with configurations that -don't interface to the PS section of the part. Changing this value has no -effect on the level shifters until the next device reconfiguration. +PL section has been reconfigured. +This variable is 1 by default but setting it to 0 allows the PL section to be +programmed with configurations that don't interface to the PS section of the +part. +Changing this value has no effect on the level shifters until the next device +reconfiguration. .Sh FILES /dev/devcfg Character device for .Nm
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