Date: Fri, 18 May 2018 14:30:46 +0000 (UTC) From: Ed Maste <emaste@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r333794 - head/sys/dev/usb/net Message-ID: <201805181430.w4IEUkSr097660@repo.freebsd.org>
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Author: emaste Date: Fri May 18 14:30:45 2018 New Revision: 333794 URL: https://svnweb.freebsd.org/changeset/base/333794 Log: muge(4): sync register names with Microchip's lan7800.h Microchip provided a permissively-licensed lan78xx header, which has an 'ETH_' prefix on most definitions. Follow suit in our driver. Sponsored by: The FreeBSD Foundation Modified: head/sys/dev/usb/net/if_muge.c head/sys/dev/usb/net/if_mugereg.h Modified: head/sys/dev/usb/net/if_muge.c ============================================================================== --- head/sys/dev/usb/net/if_muge.c Fri May 18 14:14:04 2018 (r333793) +++ head/sys/dev/usb/net/if_muge.c Fri May 18 14:30:45 2018 (r333794) @@ -171,7 +171,7 @@ struct muge_softc { uint32_t sc_rfe_ctl; uint32_t sc_mdix_ctl; uint32_t sc_rev_id; - uint32_t sc_mchash_table[DP_SEL_VHF_HASH_LEN]; + uint32_t sc_mchash_table[ETH_DP_SEL_VHF_HASH_LEN]; uint32_t sc_pfilter_table[MUGE_NUM_PFILTER_ADDRS_][2]; uint32_t sc_flags; @@ -385,13 +385,13 @@ lan78xx_eeprom_read_raw(struct muge_softc *sc, uint16_ if (!locked) MUGE_LOCK(sc); - err = lan78xx_read_reg(sc, HW_CFG, &val); + err = lan78xx_read_reg(sc, ETH_HW_CFG, &val); saved = val; - val &= ~(HW_CFG_LEDO_EN_ | HW_CFG_LED1_EN_); - err = lan78xx_write_reg(sc, HW_CFG, val); + val &= ~(ETH_HW_CFG_LEDO_EN_ | ETH_HW_CFG_LED1_EN_); + err = lan78xx_write_reg(sc, ETH_HW_CFG, val); - err = lan78xx_wait_for_bits(sc, E2P_CMD, E2P_CMD_BUSY_); + err = lan78xx_wait_for_bits(sc, ETH_E2P_CMD, ETH_E2P_CMD_BUSY_); if (err != 0) { muge_warn_printf(sc, "eeprom busy, failed to read data\n"); goto done; @@ -399,28 +399,30 @@ lan78xx_eeprom_read_raw(struct muge_softc *sc, uint16_ /* Start reading the bytes, one at a time. */ for (i = 0; i < buflen; i++) { - val = E2P_CMD_BUSY_ | E2P_CMD_READ_; - val |= (E2P_CMD_ADDR_MASK_ & (off + i)); - if ((err = lan78xx_write_reg(sc, E2P_CMD, val)) != 0) + val = ETH_E2P_CMD_BUSY_ | ETH_E2P_CMD_READ_; + val |= (ETH_E2P_CMD_ADDR_MASK_ & (off + i)); + if ((err = lan78xx_write_reg(sc, ETH_E2P_CMD, val)) != 0) goto done; start_ticks = (usb_ticks_t)ticks; do { - if ((err = lan78xx_read_reg(sc, E2P_CMD, &val)) != 0) + if ((err = lan78xx_read_reg(sc, ETH_E2P_CMD, &val)) != + 0) goto done; - if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) + if (!(val & ETH_E2P_CMD_BUSY_) || + (val & ETH_E2P_CMD_TIMEOUT_)) break; uether_pause(&sc->sc_ue, hz / 100); } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); - if (val & (E2P_CMD_BUSY_ | E2P_CMD_TIMEOUT_)) { + if (val & (ETH_E2P_CMD_BUSY_ | ETH_E2P_CMD_TIMEOUT_)) { muge_warn_printf(sc, "eeprom command failed\n"); err = USB_ERR_IOERROR; break; } - if ((err = lan78xx_read_reg(sc, E2P_DATA, &val)) != 0) + if ((err = lan78xx_read_reg(sc, ETH_E2P_DATA, &val)) != 0) goto done; buf[i] = (val & 0xff); @@ -429,7 +431,7 @@ lan78xx_eeprom_read_raw(struct muge_softc *sc, uint16_ done: if (!locked) MUGE_UNLOCK(sc); - lan78xx_write_reg(sc, HW_CFG, saved); + lan78xx_write_reg(sc, ETH_HW_CFG, saved); return (err); } @@ -450,8 +452,8 @@ lan78xx_eeprom_read(struct muge_softc *sc, uint16_t of uint8_t sig; int ret; - ret = lan78xx_eeprom_read_raw(sc, E2P_INDICATOR_OFFSET, &sig, 1); - if ((ret == 0) && (sig == E2P_INDICATOR)) { + ret = lan78xx_eeprom_read_raw(sc, ETH_E2P_INDICATOR_OFFSET, &sig, 1); + if ((ret == 0) && (sig == ETH_E2P_INDICATOR)) { ret = lan78xx_eeprom_read_raw(sc, off, buf, buflen); muge_dbg_printf(sc, "EEPROM present\n"); } else { @@ -587,11 +589,11 @@ lan78xx_setmacaddress(struct muge_softc *sc, const uin MUGE_LOCK_ASSERT(sc, MA_OWNED); val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; - if ((err = lan78xx_write_reg(sc, RX_ADDRL, val)) != 0) + if ((err = lan78xx_write_reg(sc, ETH_RX_ADDRL, val)) != 0) goto done; val = (addr[5] << 8) | addr[4]; - err = lan78xx_write_reg(sc, RX_ADDRH, val); + err = lan78xx_write_reg(sc, ETH_RX_ADDRH, val); done: return (err); @@ -617,26 +619,26 @@ lan78xx_set_rx_max_frame_length(struct muge_softc *sc, /* first we have to disable rx before changing the length */ - err = lan78xx_read_reg(sc, MAC_RX, &buf); - rxenabled = ((buf & MAC_RX_EN_) != 0); + err = lan78xx_read_reg(sc, ETH_MAC_RX, &buf); + rxenabled = ((buf & ETH_MAC_RX_EN_) != 0); if (rxenabled) { - buf &= ~MAC_RX_EN_; - err = lan78xx_write_reg(sc, MAC_RX, buf); + buf &= ~ETH_MAC_RX_EN_; + err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); } /* setting max frame length */ - buf &= ~MAC_RX_MAX_FR_SIZE_MASK_; - buf |= (((size + 4) << MAC_RX_MAX_FR_SIZE_SHIFT_) & - MAC_RX_MAX_FR_SIZE_MASK_); - err = lan78xx_write_reg(sc, MAC_RX, buf); + buf &= ~ETH_MAC_RX_MAX_FR_SIZE_MASK_; + buf |= (((size + 4) << ETH_MAC_RX_MAX_FR_SIZE_SHIFT_) & + ETH_MAC_RX_MAX_FR_SIZE_MASK_); + err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); /* If it were enabled before, we enable it back. */ if (rxenabled) { - buf |= MAC_RX_EN_; - err = lan78xx_write_reg(sc, MAC_RX, buf); + buf |= ETH_MAC_RX_EN_; + err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); } return 0; @@ -667,20 +669,23 @@ lan78xx_miibus_readreg(device_t dev, int phy, int reg) if (!locked) MUGE_LOCK(sc); - if (lan78xx_wait_for_bits(sc, MII_ACCESS, MII_BUSY_) != 0) { + if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != + 0) { muge_warn_printf(sc, "MII is busy\n"); goto done; } - addr = (phy << 11) | (reg << 6) | MII_READ_ | MII_BUSY_; - lan78xx_write_reg(sc, MII_ACCESS, addr); + addr = (phy << 11) | (reg << 6) | + ETH_MII_ACC_MII_READ_ | ETH_MII_ACC_MII_BUSY_; + lan78xx_write_reg(sc, ETH_MII_ACC, addr); - if (lan78xx_wait_for_bits(sc, MII_ACCESS, MII_BUSY_) != 0) { + if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != + 0) { muge_warn_printf(sc, "MII read timeout\n"); goto done; } - lan78xx_read_reg(sc, MII_DATA, &val); + lan78xx_read_reg(sc, ETH_MII_DATA, &val); val = le32toh(val); done: @@ -719,18 +724,19 @@ lan78xx_miibus_writereg(device_t dev, int phy, int reg if (!locked) MUGE_LOCK(sc); - if (lan78xx_wait_for_bits(sc, MII_ACCESS, MII_BUSY_) != 0) { + if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != + 0) { muge_warn_printf(sc, "MII is busy\n"); goto done; } val = htole32(val); - lan78xx_write_reg(sc, MII_DATA, val); + lan78xx_write_reg(sc, ETH_MII_DATA, val); - addr = (phy << 11) | (reg << 6) | MII_WRITE_ | MII_BUSY_; - lan78xx_write_reg(sc, MII_ACCESS, addr); + addr = (phy << 11) | (reg << 6) | ETH_MII_ACC_MII_WRITE_ | ETH_MII_ACC_MII_BUSY_; + lan78xx_write_reg(sc, ETH_MII_ACC, addr); - if (lan78xx_wait_for_bits(sc, MII_ACCESS, MII_BUSY_) != 0) + if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 0) muge_warn_printf(sc, "MII write timeout\n"); done: @@ -794,7 +800,7 @@ lan78xx_miibus_statchg(device_t dev) goto done; } - err = lan78xx_read_reg(sc, FCT_FLOW, &fct_flow); + err = lan78xx_read_reg(sc, ETH_FCT_FLOW, &fct_flow); if (err) { muge_warn_printf(sc, "failed to read initial flow control thresholds, error %d\n", @@ -808,10 +814,10 @@ lan78xx_miibus_statchg(device_t dev) /* enable transmit MAC flow control function */ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) - flow |= FLOW_CR_TX_FCEN_ | 0xFFFF; + flow |= ETH_FLOW_CR_TX_FCEN_ | 0xFFFF; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) - flow |= FLOW_CR_RX_FCEN_; + flow |= ETH_FLOW_CR_RX_FCEN_; } switch(usbd_get_speed(sc->sc_ue.ue_udev)) { @@ -825,8 +831,8 @@ lan78xx_miibus_statchg(device_t dev) break; } - err += lan78xx_write_reg(sc, FLOW, flow); - err += lan78xx_write_reg(sc, FCT_FLOW, fct_flow); + err += lan78xx_write_reg(sc, ETH_FLOW, flow); + err += lan78xx_write_reg(sc, ETH_FCT_FLOW, fct_flow); if (err) muge_warn_printf(sc, "media change failed, error %d\n", err); @@ -955,9 +961,10 @@ lan78xx_chip_init(struct muge_softc *sc) MUGE_LOCK(sc); /* Enter H/W config mode */ - lan78xx_write_reg(sc, HW_CFG, HW_CFG_LRST_); + lan78xx_write_reg(sc, ETH_HW_CFG, ETH_HW_CFG_LRST_); - if ((err = lan78xx_wait_for_bits(sc, HW_CFG, HW_CFG_LRST_)) != 0) { + if ((err = lan78xx_wait_for_bits(sc, ETH_HW_CFG, ETH_HW_CFG_LRST_)) != + 0) { muge_warn_printf(sc, "timed-out waiting for lite reset to complete\n"); goto init_failed; @@ -970,22 +977,23 @@ lan78xx_chip_init(struct muge_softc *sc) } /* Read and display the revision register */ - if ((err = lan78xx_read_reg(sc, ID_REV, &sc->sc_rev_id)) < 0) { - muge_warn_printf(sc, "failed to read ID_REV (err = %d)\n", err); + if ((err = lan78xx_read_reg(sc, ETH_ID_REV, &sc->sc_rev_id)) < 0) { + muge_warn_printf(sc, "failed to read ETH_ID_REV (err = %d)\n", + err); goto init_failed; } device_printf(sc->sc_ue.ue_dev, "chip 0x%04lx, rev. %04lx\n", - (sc->sc_rev_id & ID_REV_CHIP_ID_MASK_) >> 16, - (sc->sc_rev_id & ID_REV_CHIP_REV_MASK_)); + (sc->sc_rev_id & ETH_ID_REV_CHIP_ID_MASK_) >> 16, + (sc->sc_rev_id & ETH_ID_REV_CHIP_REV_MASK_)); /* Respond to BULK-IN tokens with a NAK when RX FIFO is empty. */ - if ((err = lan78xx_read_reg(sc, USB_CFG0, &buf)) != 0) { - muge_warn_printf(sc, "failed to read USB_CFG0: %d\n", err); + if ((err = lan78xx_read_reg(sc, ETH_USB_CFG0, &buf)) != 0) { + muge_warn_printf(sc, "failed to read ETH_USB_CFG0 (err=%d)\n", err); goto init_failed; } - buf |= USB_CFG_BIR_; - lan78xx_write_reg(sc, USB_CFG0, buf); + buf |= ETH_USB_CFG_BIR_; + lan78xx_write_reg(sc, ETH_USB_CFG0, buf); /* * LTM support will go here. @@ -1003,24 +1011,24 @@ lan78xx_chip_init(struct muge_softc *sc) burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_FS_USB_PKT_SIZE; } - lan78xx_write_reg(sc, BURST_CAP, burst_cap); + lan78xx_write_reg(sc, ETH_BURST_CAP, burst_cap); /* Set the default bulk in delay (same value from Linux driver) */ - lan78xx_write_reg(sc, BULK_IN_DLY, MUGE_DEFAULT_BULK_IN_DELAY); + lan78xx_write_reg(sc, ETH_BULK_IN_DLY, MUGE_DEFAULT_BULK_IN_DELAY); /* Multiple ethernet frames per USB packets */ - err = lan78xx_read_reg(sc, HW_CFG, &buf); - buf |= HW_CFG_MEF_; - err = lan78xx_write_reg(sc, HW_CFG, buf); + err = lan78xx_read_reg(sc, ETH_HW_CFG, &buf); + buf |= ETH_HW_CFG_MEF_; + err = lan78xx_write_reg(sc, ETH_HW_CFG, buf); /* Enable burst cap. */ - if ((err = lan78xx_read_reg(sc, USB_CFG0, &buf)) < 0) { - muge_warn_printf(sc, "failed to read USB_CFG0: (err = %d)\n", + if ((err = lan78xx_read_reg(sc, ETH_USB_CFG0, &buf)) < 0) { + muge_warn_printf(sc, "failed to read ETH_USB_CFG0 (err=%d)\n", err); goto init_failed; } - buf |= USB_CFG_BCE_; - err = lan78xx_write_reg(sc, USB_CFG0, buf); + buf |= ETH_USB_CFG_BCE_; + err = lan78xx_write_reg(sc, ETH_USB_CFG0, buf); /* * Set FCL's RX and TX FIFO sizes: according to data sheet this is @@ -1030,28 +1038,28 @@ lan78xx_chip_init(struct muge_softc *sc) */ buf = (MUGE_MAX_RX_FIFO_SIZE - 512) / 512; - err = lan78xx_write_reg(sc, FCT_RX_FIFO_END, buf); + err = lan78xx_write_reg(sc, ETH_FCT_RX_FIFO_END, buf); buf = (MUGE_MAX_TX_FIFO_SIZE - 512) / 512; - err = lan78xx_write_reg(sc, FCT_TX_FIFO_END, buf); + err = lan78xx_write_reg(sc, ETH_FCT_TX_FIFO_END, buf); /* Enabling interrupts. (Not using them for now) */ - err = lan78xx_write_reg(sc, INT_STS, INT_STS_CLEAR_ALL_); + err = lan78xx_write_reg(sc, ETH_INT_STS, ETH_INT_STS_CLEAR_ALL_); /* * Initializing flow control registers to 0. These registers are * properly set is handled in link-reset function in the Linux driver. */ - err = lan78xx_write_reg(sc, FLOW, 0); - err = lan78xx_write_reg(sc, FCT_FLOW, 0); + err = lan78xx_write_reg(sc, ETH_FLOW, 0); + err = lan78xx_write_reg(sc, ETH_FCT_FLOW, 0); /* * Settings for the RFE, we enable broadcast and destination address * perfect filtering. */ - err = lan78xx_read_reg(sc, RFE_CTL, &buf); - buf |= RFE_CTL_BCAST_EN_ | RFE_CTL_DA_PERFECT_; - err = lan78xx_write_reg(sc, RFE_CTL, buf); + err = lan78xx_read_reg(sc, ETH_RFE_CTL, &buf); + buf |= ETH_RFE_CTL_BCAST_EN_ | ETH_RFE_CTL_DA_PERFECT_; + err = lan78xx_write_reg(sc, ETH_RFE_CTL, buf); /* * At this point the Linux driver writes multicast tables, and enables @@ -1060,41 +1068,42 @@ lan78xx_chip_init(struct muge_softc *sc) */ /* Reset the PHY. */ - lan78xx_write_reg(sc, PMT_CTL, PMT_CTL_PHY_RST_); - if ((err = lan78xx_wait_for_bits(sc, PMT_CTL, PMT_CTL_PHY_RST_)) != 0) { + lan78xx_write_reg(sc, ETH_PMT_CTL, ETH_PMT_CTL_PHY_RST_); + if ((err = lan78xx_wait_for_bits(sc, ETH_PMT_CTL, + ETH_PMT_CTL_PHY_RST_)) != 0) { muge_warn_printf(sc, "timed-out waiting for phy reset to complete\n"); goto init_failed; } /* Enable automatic duplex detection and automatic speed detection. */ - err = lan78xx_read_reg(sc, MAC_CR, &buf); - buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_; - err = lan78xx_write_reg(sc, MAC_CR, buf); + err = lan78xx_read_reg(sc, ETH_MAC_CR, &buf); + buf |= ETH_MAC_CR_AUTO_DUPLEX_ | ETH_MAC_CR_AUTO_SPEED_; + err = lan78xx_write_reg(sc, ETH_MAC_CR, buf); /* * Enable PHY interrupts (Not really getting used for now) - * INT_EP_CTL: interrupt endpoint control register + * ETH_INT_EP_CTL: interrupt endpoint control register * phy events cause interrupts to be issued */ - err = lan78xx_read_reg(sc, INT_EP_CTL, &buf); - buf |= INT_ENP_PHY_INT; - err = lan78xx_write_reg(sc, INT_EP_CTL, buf); + err = lan78xx_read_reg(sc, ETH_INT_EP_CTL, &buf); + buf |= ETH_INT_ENP_PHY_INT; + err = lan78xx_write_reg(sc, ETH_INT_EP_CTL, buf); /* * Enables mac's transmitter. It will transmit frames from the buffer * onto the cable. */ - err = lan78xx_read_reg(sc, MAC_TX, &buf); - buf |= MAC_TX_TXEN_; - err = lan78xx_write_reg(sc, MAC_TX, buf); + err = lan78xx_read_reg(sc, ETH_MAC_TX, &buf); + buf |= ETH_MAC_TX_TXEN_; + err = lan78xx_write_reg(sc, ETH_MAC_TX, buf); /* * FIFO is capable of transmitting frames to MAC. */ - err = lan78xx_read_reg(sc, FCT_TX_CTL, &buf); - buf |= FCT_TX_CTL_EN_; - err = lan78xx_write_reg(sc, FCT_TX_CTL, buf); + err = lan78xx_read_reg(sc, ETH_FCT_TX_CTL, &buf); + buf |= ETH_FCT_TX_CTL_EN_; + err = lan78xx_write_reg(sc, ETH_FCT_TX_CTL, buf); /* * Set max frame length. In linux this is dev->mtu (which by default @@ -1111,16 +1120,16 @@ lan78xx_chip_init(struct muge_softc *sc) /* * enable MAC RX */ - err = lan78xx_read_reg(sc, MAC_RX, &buf); - buf |= MAC_RX_EN_; - err = lan78xx_write_reg(sc, MAC_RX, buf); + err = lan78xx_read_reg(sc, ETH_MAC_RX, &buf); + buf |= ETH_MAC_RX_EN_; + err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); /* * enable FIFO controller RX */ - err = lan78xx_read_reg(sc, FCT_RX_CTL, &buf); - buf |= FCT_TX_CTL_EN_; - err = lan78xx_write_reg(sc, FCT_RX_CTL, buf); + err = lan78xx_read_reg(sc, ETH_FCT_RX_CTL, &buf); + buf |= ETH_FCT_TX_CTL_EN_; + err = lan78xx_write_reg(sc, ETH_FCT_RX_CTL, buf); return 0; @@ -1459,8 +1468,8 @@ muge_attach_post(struct usb_ether *ue) lan78xx_read_reg(sc, 0, &val); /* Check if there is already a MAC address in the register */ - if ((lan78xx_read_reg(sc, RX_ADDRL, &mac_l) == 0) && - (lan78xx_read_reg(sc, RX_ADDRH, &mac_h) == 0)) { + if ((lan78xx_read_reg(sc, ETH_RX_ADDRL, &mac_l) == 0) && + (lan78xx_read_reg(sc, ETH_RX_ADDRH, &mac_h) == 0)) { sc->sc_ue.ue_eaddr[5] = (uint8_t)((mac_h >> 8) & 0xff); sc->sc_ue.ue_eaddr[4] = (uint8_t)((mac_h) & 0xff); sc->sc_ue.ue_eaddr[3] = (uint8_t)((mac_l >> 24) & 0xff); @@ -1474,7 +1483,7 @@ muge_attach_post(struct usb_ether *ue) * generate a random MAC address. */ if (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr)) { - if ((lan78xx_eeprom_read(sc, E2P_MAC_OFFSET, + if ((lan78xx_eeprom_read(sc, ETH_E2P_MAC_OFFSET, sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN) == 0) || (lan78xx_otp_read(sc, OTP_MAC_OFFSET, sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN) == 0)) { @@ -1688,7 +1697,7 @@ muge_set_addr_filter(struct muge_softc *sc, int index, sc->sc_pfilter_table[index][1] = tmp; tmp = addr[5]; tmp |= addr[4] | (tmp << 8); - tmp |= PFILTER_ADDR_VALID_ | PFILTER_ADDR_TYPE_DST_; + tmp |= ETH_MAF_HI_VALID_ | ETH_MAF_HI_TYPE_DST_; sc->sc_pfilter_table[index][0] = tmp; } } @@ -1713,22 +1722,22 @@ lan78xx_dataport_write(struct muge_softc *sc, uint32_t int i, ret; MUGE_LOCK_ASSERT(sc, MA_OWNED); - ret = lan78xx_wait_for_bits(sc, DP_SEL, DP_SEL_DPRDY_); + ret = lan78xx_wait_for_bits(sc, ETH_DP_SEL, ETH_DP_SEL_DPRDY_); if (ret < 0) goto done; - ret = lan78xx_read_reg(sc, DP_SEL, &dp_sel); + ret = lan78xx_read_reg(sc, ETH_DP_SEL, &dp_sel); - dp_sel &= ~DP_SEL_RSEL_MASK_; + dp_sel &= ~ETH_DP_SEL_RSEL_MASK_; dp_sel |= ram_select; - ret = lan78xx_write_reg(sc, DP_SEL, dp_sel); + ret = lan78xx_write_reg(sc, ETH_DP_SEL, dp_sel); for (i = 0; i < length; i++) { - ret = lan78xx_write_reg(sc, DP_ADDR, addr + i); - ret = lan78xx_write_reg(sc, DP_DATA, buf[i]); - ret = lan78xx_write_reg(sc, DP_CMD, DP_CMD_WRITE_); - ret = lan78xx_wait_for_bits(sc, DP_SEL, DP_SEL_DPRDY_); + ret = lan78xx_write_reg(sc, ETH_DP_ADDR, addr + i); + ret = lan78xx_write_reg(sc, ETH_DP_DATA, buf[i]); + ret = lan78xx_write_reg(sc, ETH_DP_CMD, ETH_DP_CMD_WRITE_); + ret = lan78xx_wait_for_bits(sc, ETH_DP_SEL, ETH_DP_SEL_DPRDY_); if (ret != 0) goto done; } @@ -1749,8 +1758,9 @@ static void muge_multicast_write(struct muge_softc *sc) { int i, ret; - lan78xx_dataport_write(sc, DP_SEL_RSEL_VLAN_DA_, DP_SEL_VHF_VLAN_LEN, - DP_SEL_VHF_HASH_LEN, sc->sc_mchash_table); + lan78xx_dataport_write(sc, ETH_DP_SEL_RSEL_VLAN_DA_, + ETH_DP_SEL_VHF_VLAN_LEN, ETH_DP_SEL_VHF_HASH_LEN, + sc->sc_mchash_table); for (i = 1; i < MUGE_NUM_PFILTER_ADDRS_; i++) { ret = lan78xx_write_reg(sc, PFILTER_HI(i), 0); @@ -1798,11 +1808,11 @@ muge_setmulti(struct usb_ether *ue) MUGE_LOCK_ASSERT(sc, MA_OWNED); - sc->sc_rfe_ctl &= ~(RFE_CTL_UCAST_EN_ | RFE_CTL_MCAST_EN_ | - RFE_CTL_DA_PERFECT_ | RFE_CTL_MCAST_HASH_); + sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_UCAST_EN_ | ETH_RFE_CTL_MCAST_EN_ | + ETH_RFE_CTL_DA_PERFECT_ | ETH_RFE_CTL_MCAST_HASH_); /* Initializing hash filter table */ - for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++) + for (i = 0; i < ETH_DP_SEL_VHF_HASH_LEN; i++) sc->sc_mchash_table[i] = 0; /* Initializing perfect filter table */ @@ -1811,14 +1821,14 @@ muge_setmulti(struct usb_ether *ue) sc->sc_pfilter_table[i][1] = 0; } - sc->sc_rfe_ctl |= RFE_CTL_BCAST_EN_; + sc->sc_rfe_ctl |= ETH_RFE_CTL_BCAST_EN_; if (ifp->if_flags & IFF_PROMISC) { muge_dbg_printf(sc, "promiscuous mode enabled\n"); - sc->sc_rfe_ctl |= RFE_CTL_MCAST_EN_ | RFE_CTL_UCAST_EN_; + sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_UCAST_EN_; } else if (ifp->if_flags & IFF_ALLMULTI){ muge_dbg_printf(sc, "receive all multicast enabled\n"); - sc->sc_rfe_ctl |= RFE_CTL_MCAST_EN_; + sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_; } else { /* * Take the lock of the mac address list before hashing each of @@ -1840,7 +1850,8 @@ muge_setmulti(struct usb_ether *ue) uint32_t bitnum = muge_hash(addr); sc->sc_mchash_table[bitnum / 32] |= (1 << (bitnum % 32)); - sc->sc_rfe_ctl |= RFE_CTL_MCAST_HASH_; + sc->sc_rfe_ctl |= + ETH_RFE_CTL_MCAST_HASH_; } i++; } @@ -1848,7 +1859,7 @@ muge_setmulti(struct usb_ether *ue) if_maddr_runlock(ifp); muge_multicast_write(sc); } - lan78xx_write_reg(sc, RFE_CTL, sc->sc_rfe_ctl); + lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); } /** @@ -1870,11 +1881,11 @@ muge_setpromisc(struct usb_ether *ue) MUGE_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_flags & IFF_PROMISC) - sc->sc_rfe_ctl |= RFE_CTL_MCAST_EN_ | RFE_CTL_UCAST_EN_; + sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_UCAST_EN_; else - sc->sc_rfe_ctl &= ~(RFE_CTL_MCAST_EN_); + sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_MCAST_EN_); - lan78xx_write_reg(sc, RFE_CTL, sc->sc_rfe_ctl); + lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); } /** @@ -1898,19 +1909,22 @@ static int muge_sethwcsum(struct muge_softc *sc) MUGE_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_capabilities & IFCAP_RXCSUM) { - sc->sc_rfe_ctl |= RFE_CTL_IGMP_COE_ | RFE_CTL_ICMP_COE_; - sc->sc_rfe_ctl |= RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_; + sc->sc_rfe_ctl |= ETH_RFE_CTL_IGMP_COE_ | ETH_RFE_CTL_ICMP_COE_; + sc->sc_rfe_ctl |= ETH_RFE_CTL_TCPUDP_COE_ | ETH_RFE_CTL_IP_COE_; } else { - sc->sc_rfe_ctl &= ~(RFE_CTL_IGMP_COE_ | RFE_CTL_ICMP_COE_); - sc->sc_rfe_ctl &= ~(RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_); + sc->sc_rfe_ctl &= + ~(ETH_RFE_CTL_IGMP_COE_ | ETH_RFE_CTL_ICMP_COE_); + sc->sc_rfe_ctl &= + ~(ETH_RFE_CTL_TCPUDP_COE_ | ETH_RFE_CTL_IP_COE_); } - sc->sc_rfe_ctl &= ~RFE_CTL_VLAN_FILTER_; + sc->sc_rfe_ctl &= ~ETH_RFE_CTL_VLAN_FILTER_; - err = lan78xx_write_reg(sc, RFE_CTL, sc->sc_rfe_ctl); + err = lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); if (err != 0) { - muge_warn_printf(sc, "failed to write RFE_CTL (err=%d)\n", err); + muge_warn_printf(sc, "failed to write ETH_RFE_CTL (err=%d)\n", + err); return (err); } Modified: head/sys/dev/usb/net/if_mugereg.h ============================================================================== --- head/sys/dev/usb/net/if_mugereg.h Fri May 18 14:14:04 2018 (r333793) +++ head/sys/dev/usb/net/if_mugereg.h Fri May 18 14:30:45 2018 (r333794) @@ -39,89 +39,89 @@ #define _IF_MUGEREG_H_ /* USB Vendor Requests */ -#define UVR_WRITE_REG 0xA0 -#define UVR_READ_REG 0xA1 -#define UVR_GET_STATS 0xA2 +#define UVR_WRITE_REG 0xA0 +#define UVR_READ_REG 0xA1 +#define UVR_GET_STATS 0xA2 /* Device ID and revision register */ -#define ID_REV 0x000 -#define ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL -#define ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL +#define ETH_ID_REV 0x000 +#define ETH_ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL +#define ETH_ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL /* Device interrupt status register. */ -#define INT_STS 0x00C -#define INT_STS_CLEAR_ALL_ 0xFFFFFFFFUL +#define ETH_INT_STS 0x00C +#define ETH_INT_STS_CLEAR_ALL_ 0xFFFFFFFFUL /* Hardware Configuration Register. */ -#define HW_CFG 0x010 -#define HW_CFG_LED3_EN_ (0x1UL << 23) -#define HW_CFG_LED2_EN_ (0x1UL << 22) -#define HW_CFG_LED1_EN_ (0x1UL << 21) -#define HW_CFG_LEDO_EN_ (0x1UL << 20) -#define HW_CFG_MEF_ (0x1UL << 4) -#define HW_CFG_ETC_ (0x1UL << 3) -#define HW_CFG_LRST_ (0x1UL << 1) /* Lite reset */ -#define HW_CFG_SRST_ (0x1UL << 0) /* Soft reset */ +#define ETH_HW_CFG 0x010 +#define ETH_HW_CFG_LED3_EN_ (0x1UL << 23) +#define ETH_HW_CFG_LED2_EN_ (0x1UL << 22) +#define ETH_HW_CFG_LED1_EN_ (0x1UL << 21) +#define ETH_HW_CFG_LEDO_EN_ (0x1UL << 20) +#define ETH_HW_CFG_MEF_ (0x1UL << 4) +#define ETH_HW_CFG_ETC_ (0x1UL << 3) +#define ETH_HW_CFG_LRST_ (0x1UL << 1) /* Lite reset */ +#define ETH_HW_CFG_SRST_ (0x1UL << 0) /* Soft reset */ /* Power Management Control Register. */ -#define PMT_CTL 0x014 -#define PMT_CTL_PHY_RST_ (0x1UL << 4) /* PHY reset */ -#define PMT_CTL_WOL_EN_ (0x1UL << 3) /* PHY wake-on-lan enable */ -#define PMT_CTL_PHY_WAKE_EN_ (0x1UL << 2) /* PHY interrupt as a wake up event*/ +#define ETH_PMT_CTL 0x014 +#define ETH_PMT_CTL_PHY_RST_ (0x1UL << 4) /* PHY reset */ +#define ETH_PMT_CTL_WOL_EN_ (0x1UL << 3) /* PHY wake-on-lan */ +#define ETH_PMT_CTL_PHY_WAKE_EN_ (0x1UL << 2) /* PHY int wake */ /* GPIO Configuration 0 Register. */ -#define GPIO_CFG0 0x018 +#define ETH_GPIO_CFG0 0x018 /* GPIO Configuration 1 Register. */ -#define GPIO_CFG1 0x01C +#define ETH_GPIO_CFG1 0x01C /* GPIO wake enable and polarity register. */ -#define GPIO_WAKE 0x020 +#define ETH_GPIO_WAKE 0x020 /* RX Command A */ -#define RX_CMD_A_RED_ (0x1UL << 22) /* Receive Error Detected */ -#define RX_CMD_A_ICSM_ (0x1UL << 14) -#define RX_CMD_A_LEN_MASK_ 0x00003FFFUL +#define RX_CMD_A_RED_ (0x1UL << 22) /* Receive Error Det */ +#define RX_CMD_A_ICSM_ (0x1UL << 14) +#define RX_CMD_A_LEN_MASK_ 0x00003FFFUL /* TX Command A */ -#define TX_CMD_A_LEN_MASK_ 0x000FFFFFUL -#define TX_CMD_A_FCS_ (0x1UL << 22) +#define TX_CMD_A_LEN_MASK_ 0x000FFFFFUL +#define TX_CMD_A_FCS_ (0x1UL << 22) /* Data Port Select Register */ -#define DP_SEL 0x024 -#define DP_SEL_DPRDY_ (0x1UL << 31) -#define DP_SEL_RSEL_VLAN_DA_ (0x1UL << 0) /* RFE VLAN and DA Hash Table */ -#define DP_SEL_RSEL_MASK_ 0x0000000F -#define DP_SEL_VHF_HASH_LEN 16 -#define DP_SEL_VHF_VLAN_LEN 128 +#define ETH_DP_SEL 0x024 +#define ETH_DP_SEL_DPRDY_ (0x1UL << 31) +#define ETH_DP_SEL_RSEL_VLAN_DA_ (0x1UL << 0) /* RFE VLAN/DA Hash */ +#define ETH_DP_SEL_RSEL_MASK_ 0x0000000F +#define ETH_DP_SEL_VHF_HASH_LEN 16 +#define ETH_DP_SEL_VHF_VLAN_LEN 128 /* Data Port Command Register */ -#define DP_CMD 0x028 -#define DP_CMD_WRITE_ (0x1UL << 0) /* 1 for write */ -#define DP_CMD_READ_ (0x0UL << 0) /* 0 for read */ +#define ETH_DP_CMD 0x028 +#define ETH_DP_CMD_WRITE_ (0x1UL << 0) /* 1 for write */ +#define ETH_DP_CMD_READ_ (0x0UL << 0) /* 0 for read */ /* Data Port Address Register */ -#define DP_ADDR 0x02C +#define ETH_DP_ADDR 0x02C /* Data Port Data Register */ -#define DP_DATA 0x030 +#define ETH_DP_DATA 0x030 /* EEPROM Command Register */ -#define E2P_CMD 0x040 -#define E2P_CMD_MASK_ 0x70000000UL -#define E2P_CMD_ADDR_MASK_ 0x000001FFUL -#define E2P_CMD_BUSY_ (0x1UL << 31) -#define E2P_CMD_READ_ (0x0UL << 28) -#define E2P_CMD_WRITE_ (0x3UL << 28) -#define E2P_CMD_ERASE_ (0x5UL << 28) -#define E2P_CMD_RELOAD_ (0x7UL << 28) -#define E2P_CMD_TIMEOUT_ (0x1UL << 10) -#define E2P_MAC_OFFSET 0x01 -#define E2P_INDICATOR_OFFSET 0x00 +#define ETH_E2P_CMD 0x040 +#define ETH_E2P_CMD_MASK_ 0x70000000UL +#define ETH_E2P_CMD_ADDR_MASK_ 0x000001FFUL +#define ETH_E2P_CMD_BUSY_ (0x1UL << 31) +#define ETH_E2P_CMD_READ_ (0x0UL << 28) +#define ETH_E2P_CMD_WRITE_ (0x3UL << 28) +#define ETH_E2P_CMD_ERASE_ (0x5UL << 28) +#define ETH_E2P_CMD_RELOAD_ (0x7UL << 28) +#define ETH_E2P_CMD_TIMEOUT_ (0x1UL << 10) +#define ETH_E2P_MAC_OFFSET 0x01 +#define ETH_E2P_INDICATOR_OFFSET 0x00 /* EEPROM Data Register */ -#define E2P_DATA 0x044 -#define E2P_INDICATOR 0xA5 /* Indicates an EEPROM is present */ +#define ETH_E2P_DATA 0x044 +#define ETH_E2P_INDICATOR 0xA5 /* EEPROM is present */ /* Packet sizes. */ #define MUGE_SS_USB_PKT_SIZE 1024 @@ -129,60 +129,60 @@ #define MUGE_FS_USB_PKT_SIZE 64 /* Receive Filtering Engine Control Register */ -#define RFE_CTL 0x0B0 -#define RFE_CTL_IGMP_COE_ (0x1U << 14) -#define RFE_CTL_ICMP_COE_ (0x1U << 13) -#define RFE_CTL_TCPUDP_COE_ (0x1U << 12) -#define RFE_CTL_IP_COE_ (0x1U << 11) -#define RFE_CTL_BCAST_EN_ (0x1U << 10) -#define RFE_CTL_MCAST_EN_ (0x1U << 9) -#define RFE_CTL_UCAST_EN_ (0x1U << 8) -#define RFE_CTL_VLAN_FILTER_ (0x1U << 5) -#define RFE_CTL_MCAST_HASH_ (0x1U << 3) -#define RFE_CTL_DA_PERFECT_ (0x1U << 1) +#define ETH_RFE_CTL 0x0B0 +#define ETH_RFE_CTL_IGMP_COE_ (0x1U << 14) +#define ETH_RFE_CTL_ICMP_COE_ (0x1U << 13) +#define ETH_RFE_CTL_TCPUDP_COE_ (0x1U << 12) +#define ETH_RFE_CTL_IP_COE_ (0x1U << 11) +#define ETH_RFE_CTL_BCAST_EN_ (0x1U << 10) +#define ETH_RFE_CTL_MCAST_EN_ (0x1U << 9) +#define ETH_RFE_CTL_UCAST_EN_ (0x1U << 8) +#define ETH_RFE_CTL_VLAN_FILTER_ (0x1U << 5) +#define ETH_RFE_CTL_MCAST_HASH_ (0x1U << 3) +#define ETH_RFE_CTL_DA_PERFECT_ (0x1U << 1) /* End address of the RX FIFO */ -#define FCT_RX_FIFO_END 0x0C8 -#define FCT_RX_FIFO_END_MASK_ 0x0000007FUL +#define ETH_FCT_RX_FIFO_END 0x0C8 +#define ETH_FCT_RX_FIFO_END_MASK_ 0x0000007FUL #define MUGE_MAX_RX_FIFO_SIZE (12 * 1024) /* End address of the TX FIFO */ -#define FCT_TX_FIFO_END 0x0CC -#define FCT_TX_FIFO_END_MASK_ 0x0000003FUL +#define ETH_FCT_TX_FIFO_END 0x0CC +#define ETH_FCT_TX_FIFO_END_MASK_ 0x0000003FUL #define MUGE_MAX_TX_FIFO_SIZE (12 * 1024) /* USB Configuration Register 0 */ -#define USB_CFG0 0x080 -#define USB_CFG_BIR_ (0x1U << 6) /* Bulk-In Empty response */ -#define USB_CFG_BCE_ (0x1U << 5) /* Burst Cap Enable */ +#define ETH_USB_CFG0 0x080 +#define ETH_USB_CFG_BIR_ (0x1U << 6) /* Bulk-In Empty resp */ +#define ETH_USB_CFG_BCE_ (0x1U << 5) /* Burst Cap Enable */ /* USB Configuration Register 1 */ -#define USB_CFG1 0x084 +#define ETH_USB_CFG1 0x084 /* USB Configuration Register 2 */ -#define USB_CFG2 0x088 +#define ETH_USB_CFG2 0x088 /* USB bConfigIndex: it only has one configuration. */ -#define MUGE_CONFIG_INDEX 0 +#define MUGE_CONFIG_INDEX 0 /* Burst Cap Register */ -#define BURST_CAP 0x090 +#define ETH_BURST_CAP 0x090 #define MUGE_DEFAULT_BURST_CAP_SIZE MUGE_MAX_TX_FIFO_SIZE /* Bulk-In Delay Register */ -#define BULK_IN_DLY 0x094 -#define MUGE_DEFAULT_BULK_IN_DELAY 0x0800 +#define ETH_BULK_IN_DLY 0x094 +#define MUGE_DEFAULT_BULK_IN_DELAY 0x0800 /* Interrupt Endpoint Control Register */ -#define INT_EP_CTL 0x098 -#define INT_ENP_PHY_INT (0x1U << 17) /* PHY Enable */ +#define ETH_INT_EP_CTL 0x098 +#define ETH_INT_ENP_PHY_INT (0x1U << 17) /* PHY Enable */ /* Registers on the phy, accessed via MII/MDIO */ -#define MUGE_PHY_INTR_STAT 25 -#define MUGE_PHY_INTR_MASK 26 -#define MUGE_PHY_INTR_LINK_CHANGE (0x1U << 13) +#define MUGE_PHY_INTR_STAT 25 +#define MUGE_PHY_INTR_MASK 26 +#define MUGE_PHY_INTR_LINK_CHANGE (0x1U << 13) #define MUGE_PHY_INTR_ANEG_COMP (0x1U << 10) -#define MUGE_EXT_PAGE_ACCESS 0x1F +#define MUGE_EXT_PAGE_ACCESS 0x1F #define MUGE_EXT_PAGE_SPACE_0 0x0000 #define MUGE_EXT_PAGE_SPACE_1 0x0001 #define MUGE_EXT_PAGE_SPACE_2 0x0002 @@ -193,58 +193,58 @@ #define MUGE_EXT_MODE_CTRL_AUTO_MDIX_ 0x0000 /* FCT Flow Control Threshold Register */ -#define FCT_FLOW 0x0D0 +#define ETH_FCT_FLOW 0x0D0 /* FCT RX FIFO Control Register */ -#define FCT_RX_CTL 0x0C0 +#define ETH_FCT_RX_CTL 0x0C0 /* FCT TX FIFO Control Register */ -#define FCT_TX_CTL 0x0C4 -#define FCT_TX_CTL_EN_ (0x1U << 31) +#define ETH_FCT_TX_CTL 0x0C4 +#define ETH_FCT_TX_CTL_EN_ (0x1U << 31) /* MAC Control Register */ -#define MAC_CR 0x100 -#define MAC_CR_AUTO_DUPLEX_ (0x1U << 12) -#define MAC_CR_AUTO_SPEED_ (0x1U << 11) +#define ETH_MAC_CR 0x100 +#define ETH_MAC_CR_AUTO_DUPLEX_ (0x1U << 12) +#define ETH_MAC_CR_AUTO_SPEED_ (0x1U << 11) /* MAC Receive Register */ -#define MAC_RX 0x104 -#define MAC_RX_MAX_FR_SIZE_MASK_ 0x3FFF0000 -#define MAC_RX_MAX_FR_SIZE_SHIFT_ 16 -#define MAC_RX_EN_ (0x1U << 0) /* Enable Receiver */ +#define ETH_MAC_RX 0x104 +#define ETH_MAC_RX_MAX_FR_SIZE_MASK_ 0x3FFF0000 +#define ETH_MAC_RX_MAX_FR_SIZE_SHIFT_ 16 +#define ETH_MAC_RX_EN_ (0x1U << 0) /* Enable Receiver */ /* MAC Transmit Register */ -#define MAC_TX 0x108 -#define MAC_TX_TXEN_ (0x1U << 0) /* Enable Transmitter */ +#define ETH_MAC_TX 0x108 +#define ETH_MAC_TX_TXEN_ (0x1U << 0) /* Enable Transmitter */ /* Flow Control Register */ -#define FLOW 0x10C -#define FLOW_CR_TX_FCEN_ (0x1U << 30) /* TX FC Enable */ -#define FLOW_CR_RX_FCEN_ (0x1U << 29) /* RX FC Enable */ +#define ETH_FLOW 0x10C +#define ETH_FLOW_CR_TX_FCEN_ (0x1U << 30) /* TX FC Enable */ +#define ETH_FLOW_CR_RX_FCEN_ (0x1U << 29) /* RX FC Enable */ /* MAC Receive Address Registers */ -#define RX_ADDRH 0x118 /* High */ -#define RX_ADDRL 0x11C /* Low */ +#define ETH_RX_ADDRH 0x118 /* High */ +#define ETH_RX_ADDRL 0x11C /* Low */ /* MII Access Register */ -#define MII_ACCESS 0x120 -#define MII_BUSY_ (0x1UL << 0) -#define MII_READ_ (0x0UL << 1) -#define MII_WRITE_ (0x1UL << 1) +#define ETH_MII_ACC 0x120 +#define ETH_MII_ACC_MII_BUSY_ (0x1UL << 0) +#define ETH_MII_ACC_MII_READ_ (0x0UL << 1) +#define ETH_MII_ACC_MII_WRITE_ (0x1UL << 1) /* MII Data Register */ -#define MII_DATA 0x124 +#define ETH_MII_DATA 0x124 /* MAC address perfect filter registers (ADDR_FILTx) */ -#define PFILTER_BASE 0x400 -#define PFILTER_HIX 0x00 -#define PFILTER_LOX 0x04 +#define ETH_MAF_BASE 0x400 +#define ETH_MAF_HIx 0x00 +#define ETH_MAF_LOx 0x04 #define MUGE_NUM_PFILTER_ADDRS_ 33 -#define PFILTER_ADDR_VALID_ (0x1UL << 31) -#define PFILTER_ADDR_TYPE_SRC_ (0x1UL << 30) -#define PFILTER_ADDR_TYPE_DST_ (0x0UL << 30) -#define PFILTER_HI(index) (PFILTER_BASE + (8 * (index)) + (PFILTER_HIX)) -#define PFILTER_LO(index) (PFILTER_BASE + (8 * (index)) + (PFILTER_LOX)) +#define ETH_MAF_HI_VALID_ (0x1UL << 31) +#define ETH_MAF_HI_TYPE_SRC_ (0x1UL << 30) +#define ETH_MAF_HI_TYPE_DST_ (0x0UL << 30) +#define PFILTER_HI(index) (ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_HIx)) +#define PFILTER_LO(index) (ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_LOx)) /* * These registers are not documented in the datasheet, and are based on @@ -276,82 +276,97 @@ /* Some unused registers, from the data sheet. */ #if 0 -#define BOS_ATTR 0x050 -#define SS_ATTR 0x054 -#define HS_ATTR 0x058 -#define FS_ATTR 0x05C -#define STRNG_ATTR0 0x060 -#define STRNG_ATTR1 0x064 -#define FLAG_ATTR 0x068 -#define SW_GP_1 0x06C -#define SW_GP_2 0x070 -#define SW_GP_3 0x074 -#define VLAN_TYPE 0x0B4 -#define RX_DP_STOR 0x0D4 -#define TX_DP_STOR 0x0D8 -#define LTM_BELT_IDLE0 0x0E0 -#define LTM_BELT_IDLE1 0x0E4 -#define LTM_BELT_ACT0 0x0E8 -#define LTM_BELT_ACT1 0x0EC -#define LTM_INACTIVE0 0x0F0 -#define LTM_INACTIVE1 0x0F4 +#define ETH_BOS_ATTR 0x050 +#define ETH_SS_ATTR 0x054 +#define ETH_HS_ATTR 0x058 +#define ETH_FS_ATTR 0x05C +#define ETH_STRNG_ATTR0 0x060 +#define ETH_STRNG_ATTR1 0x064 +#define ETH_STRNGFLAG_ATTR 0x068 +#define ETH_SW_GP_0 0x06C +#define ETH_SW_GP_1 0x070 +#define ETH_SW_GP_2 0x074 +#define ETH_VLAN_TYPE 0x0B4 +#define ETH_RX_DP_STOR 0x0D4 +#define ETH_TX_DP_STOR 0x0D8 +#define ETH_LTM_BELT_IDLE0 0x0E0 +#define ETH_LTM_BELT_IDLE1 0x0E4 +#define ETH_LTM_BELT_ACT0 0x0E8 +#define ETH_LTM_BELT_ACT1 0x0EC +#define ETH_LTM_INACTIVE0 0x0F0 +#define ETH_LTM_INACTIVE1 0x0F4 -#define RAND_SEED 0x110 -#define ERR_STS 0x114 +#define ETH_RAND_SEED 0x110 +#define ETH_ERR_STS 0x114 -#define EEE_TX_LPI_REQUEST_DELAY_CNT 0x130 -#define EEE_TW_TX_SYS 0x134 -#define EEE_TX_LPI_AUTO_REMOVAL_DELAY 0x138 +#define ETH_EEE_TX_LPI_REQ_DLY 0x130 +#define ETH_EEE_TW_TX_SYS 0x134 +#define ETH_EEE_TX_LPI_REM_DLY 0x138 -#define WUCSR1 0x140 -#define WK_SRC 0x144 -#define WUF_CFG_BASE 0x150 -#define WUF_MASK_BASE 0x200 -#define WUCSR2 0x600 +#define ETH_WUCSR1 0x140 +#define ETH_WK_SRC 0x144 +#define ETH_WUF_CFGx 0x150 +#define ETH_WUF_MASKx 0x200 +#define ETH_WUCSR2 0x600 -#define NSx_IPV6_ADDR_DEST_0 0x610 -#define NSx_IPV6_ADDR_DEST_1 0x614 -#define NSx_IPV6_ADDR_DEST_2 0x618 -#define NSx_IPV6_ADDR_DEST_3 0x61C +#define ETH_NS1_IPV6_ADDR_DEST0 0x610 +#define ETH_NS1_IPV6_ADDR_DEST1 0x614 +#define ETH_NS1_IPV6_ADDR_DEST2 0x618 +#define ETH_NS1_IPV6_ADDR_DEST3 0x61C -#define NSx_IPV6_ADDR_SRC_0 0x620 -#define NSx_IPV6_ADDR_SRC_1 0x624 -#define NSx_IPV6_ADDR_SRC_2 0x628 -#define NSx_IPV6_ADDR_SRC_3 0x62C +#define ETH_NS1_IPV6_ADDR_SRC0 0x620 +#define ETH_NS1_IPV6_ADDR_SRC1 0x624 +#define ETH_NS1_IPV6_ADDR_SRC2 0x628 +#define ETH_NS1_IPV6_ADDR_SRC3 0x62C *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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