From owner-svn-src-projects@FreeBSD.ORG Wed Aug 31 08:27:42 2011 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 22235106564A; Wed, 31 Aug 2011 08:27:42 +0000 (UTC) (envelope-from gber@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id B2AF68FC0C; Wed, 31 Aug 2011 08:27:41 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p7V8RfBD090089; Wed, 31 Aug 2011 08:27:41 GMT (envelope-from gber@svn.freebsd.org) Received: (from gber@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p7V8RfcF090087; Wed, 31 Aug 2011 08:27:41 GMT (envelope-from gber@svn.freebsd.org) Message-Id: <201108310827.p7V8RfcF090087@svn.freebsd.org> From: Grzegorz Bernacki Date: Wed, 31 Aug 2011 08:27:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r225286 - projects/armv6/sys/arm/arm X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 31 Aug 2011 08:27:42 -0000 Author: gber Date: Wed Aug 31 08:27:41 2011 New Revision: 225286 URL: http://svn.freebsd.org/changeset/base/225286 Log: Refactor ARM9E/ARM10 cpufunc initialization. Obtained from: Marvell, Semihalf Modified: projects/armv6/sys/arm/arm/cpufunc.c Modified: projects/armv6/sys/arm/arm/cpufunc.c ============================================================================== --- projects/armv6/sys/arm/arm/cpufunc.c Wed Aug 31 07:46:36 2011 (r225285) +++ projects/armv6/sys/arm/arm/cpufunc.c Wed Aug 31 08:27:41 2011 (r225286) @@ -1270,40 +1270,33 @@ set_cpufuncs() } #endif /* CPU_ARM9 */ #if defined(CPU_ARM9E) || defined(CPU_ARM10) - if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM1026EJS || - cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD || + if (cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD || cputype == CPU_ID_MV88FR571_41) { - if (cputype == CPU_ID_MV88FR131 || - cputype == CPU_ID_MV88FR571_VD || - cputype == CPU_ID_MV88FR571_41) { - - cpufuncs = sheeva_cpufuncs; - /* - * Workaround for Marvell MV78100 CPU: Cache prefetch - * mechanism may affect the cache coherency validity, - * so it needs to be disabled. - * - * Refer to errata document MV-S501058-00C.pdf (p. 3.1 - * L2 Prefetching Mechanism) for details. - */ - if (cputype == CPU_ID_MV88FR571_VD || - cputype == CPU_ID_MV88FR571_41) { - sheeva_control_ext(0xffffffff, - FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN | - FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN | - FC_L2_PREF_DIS); - } else { - sheeva_control_ext(0xffffffff, - FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN | - FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN); - } + uint32_t sheeva_ctrl; + + sheeva_ctrl = (MV_DC_STREAM_ENABLE | MV_BTB_DISABLE | + MV_L2_ENABLE); + /* + * Workaround for Marvell MV78100 CPU: Cache prefetch + * mechanism may affect the cache coherency validity, + * so it needs to be disabled. + * + * Refer to errata document MV-S501058-00C.pdf (p. 3.1 + * L2 Prefetching Mechanism) for details. + */ + if (cputype == CPU_ID_MV88FR571_VD || + cputype == CPU_ID_MV88FR571_41) + sheeva_ctrl |= MV_L2_PREFETCH_DISABLE; - /* Use powersave on this CPU. */ - cpu_do_powersave = 1; - } else - cpufuncs = armv5_ec_cpufuncs; + sheeva_control_ext(0xffffffff & ~MV_WA_ENABLE, sheeva_ctrl); - cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ + cpufuncs = sheeva_cpufuncs; + get_cachetype_cp15(); + pmap_pte_init_generic(); + goto out; + } else if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM926ES || + cputype == CPU_ID_ARM1026EJS) + cpufuncs = armv5_ec_cpufuncs; get_cachetype_cp15(); pmap_pte_init_generic(); goto out;