From owner-svn-src-head@freebsd.org Thu Dec 3 07:28:58 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id ED195A3EAC3; Thu, 3 Dec 2015 07:28:58 +0000 (UTC) (envelope-from arybchik@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id AFD6A1B33; Thu, 3 Dec 2015 07:28:58 +0000 (UTC) (envelope-from arybchik@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tB37SvmF001275; Thu, 3 Dec 2015 07:28:57 GMT (envelope-from arybchik@FreeBSD.org) Received: (from arybchik@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tB37Svcg001274; Thu, 3 Dec 2015 07:28:57 GMT (envelope-from arybchik@FreeBSD.org) Message-Id: <201512030728.tB37Svcg001274@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: arybchik set sender to arybchik@FreeBSD.org using -f From: Andrew Rybchenko Date: Thu, 3 Dec 2015 07:28:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r291680 - head/sys/dev/sfxge/common X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Dec 2015 07:28:59 -0000 Author: arybchik Date: Thu Dec 3 07:28:57 2015 New Revision: 291680 URL: https://svnweb.freebsd.org/changeset/base/291680 Log: sfxge: remove internal register definitions that should not be used by host code Submitted by: Guido Barzini Sponsored by: Solarflare Communications, Inc. MFC after: 2 days Modified: head/sys/dev/sfxge/common/efx_regs_ef10.h Modified: head/sys/dev/sfxge/common/efx_regs_ef10.h ============================================================================== --- head/sys/dev/sfxge/common/efx_regs_ef10.h Thu Dec 3 07:24:59 2015 (r291679) +++ head/sys/dev/sfxge/common/efx_regs_ef10.h Thu Dec 3 07:28:57 2015 (r291680) @@ -44,7 +44,6 @@ extern "C" { ************************************************************************** */ - /* * BIU_HW_REV_ID_REG(32bit): * @@ -190,6 +189,7 @@ extern "C" { #define ERF_DZ_TX_DESC_LWORD_LBN 0 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 + /* ES_DRIVER_EV */ #define ESF_DZ_DRV_CODE_LBN 60 #define ESF_DZ_DRV_CODE_WIDTH 4 @@ -226,1310 +226,6 @@ extern "C" { #define ESF_DZ_EV_DATA_WIDTH 60 -/* ES_FF_UMSG_CPU2DL_DESC_FETCH */ -#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 208 -#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6 -#define ESF_DZ_C2DDF_QID_LBN 160 -#define ESF_DZ_C2DDF_QID_WIDTH 11 -#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64 -#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18 -#define ESF_DZ_C2DDF_DSCR_HW_RPTR_LBN 48 -#define ESF_DZ_C2DDF_DSCR_HW_RPTR_WIDTH 12 -#define ESF_DZ_C2DDF_DSCR_HW_WPTR_LBN 32 -#define ESF_DZ_C2DDF_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_C2DDF_OID_LBN 16 -#define ESF_DZ_C2DDF_OID_WIDTH 12 -#define ESF_DZ_C2DDF_DSCR_SIZE_LBN 13 -#define ESF_DZ_C2DDF_DSCR_SIZE_WIDTH 3 -#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 -#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 -#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 -#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 -#define ESF_DZ_C2DDF_BIU_ARGS_LBN 0 -#define ESF_DZ_C2DDF_BIU_ARGS_WIDTH 13 - - -/* ES_FF_UMSG_CPU2DL_DESC_PUSH */ -#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 224 -#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 -#define ESF_DZ_C2DDP_DESC_DW0_LBN 128 -#define ESF_DZ_C2DDP_DESC_DW0_WIDTH 32 -#define ESF_DZ_C2DDP_DESC_DW1_LBN 160 -#define ESF_DZ_C2DDP_DESC_DW1_WIDTH 32 -#define ESF_DZ_C2DDP_DESC_LBN 128 -#define ESF_DZ_C2DDP_DESC_WIDTH 64 -#define ESF_DZ_C2DDP_QID_LBN 64 -#define ESF_DZ_C2DDP_QID_WIDTH 11 -#define ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32 -#define ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_C2DDP_OID_LBN 16 -#define ESF_DZ_C2DDP_OID_WIDTH 12 -#define ESF_DZ_C2DDP_DSCR_SIZE_LBN 0 -#define ESF_DZ_C2DDP_DSCR_SIZE_WIDTH 3 -#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 -#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 -#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 -#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 - - -/* ES_FF_UMSG_CPU2DL_GPRD */ -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2DG_SMC_ADDR_LBN 16 -#define ESF_DZ_C2DG_SMC_ADDR_WIDTH 16 -#define ESF_DZ_C2DG_BIU_ARGS_LBN 0 -#define ESF_DZ_C2DG_BIU_ARGS_WIDTH 14 - - -/* ES_FF_UMSG_CPU2EV_SOFT */ -#define ESF_DZ_C2ES_TBD_LBN 0 -#define ESF_DZ_C2ES_TBD_WIDTH 1 - - -/* ES_FF_UMSG_CPU2EV_TXCMPLT */ -#define ESF_DZ_C2ET_EV_SOFT2_LBN 48 -#define ESF_DZ_C2ET_EV_SOFT2_WIDTH 16 -#define ESF_DZ_C2ET_EV_CODE_LBN 42 -#define ESF_DZ_C2ET_EV_CODE_WIDTH 4 -#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_LBN 41 -#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_WIDTH 1 -#define ESF_DZ_C2ET_EV_DROP_EVENT_LBN 40 -#define ESF_DZ_C2ET_EV_DROP_EVENT_WIDTH 1 -#define ESF_DZ_C2ET_EV_CAN_MERGE_LBN 39 -#define ESF_DZ_C2ET_EV_CAN_MERGE_WIDTH 1 -#define ESF_DZ_C2ET_EV_SOFT1_LBN 32 -#define ESF_DZ_C2ET_EV_SOFT1_WIDTH 7 -#define ESF_DZ_C2ET_DSCR_IDX_LBN 16 -#define ESF_DZ_C2ET_DSCR_IDX_WIDTH 16 -#define ESF_DZ_C2ET_EV_QID_LBN 5 -#define ESF_DZ_C2ET_EV_QID_WIDTH 11 -#define ESF_DZ_C2ET_EV_QLABEL_LBN 0 -#define ESF_DZ_C2ET_EV_QLABEL_WIDTH 5 - - -/* ES_FF_UMSG_CPU2RXDP_INGR_BUFOP */ -#define ESF_DZ_C2RIB_EV_DISABLE_LBN 191 -#define ESF_DZ_C2RIB_EV_DISABLE_WIDTH 1 -#define ESF_DZ_C2RIB_EV_SOFT_LBN 188 -#define ESF_DZ_C2RIB_EV_SOFT_WIDTH 3 -#define ESF_DZ_C2RIB_EV_DESC_PTR_LBN 176 -#define ESF_DZ_C2RIB_EV_DESC_PTR_WIDTH 12 -#define ESF_DZ_C2RIB_EV_ARG1_LBN 160 -#define ESF_DZ_C2RIB_EV_ARG1_WIDTH 16 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2RIB_BIU_ARGS_LBN 16 -#define ESF_DZ_C2RIB_BIU_ARGS_WIDTH 13 -#define ESF_DZ_C2RIB_EV_QID_LBN 5 -#define ESF_DZ_C2RIB_EV_QID_WIDTH 11 -#define ESF_DZ_C2RIB_EV_QLABEL_LBN 0 -#define ESF_DZ_C2RIB_EV_QLABEL_WIDTH 5 - - -/* ES_FF_UMSG_CPU2RXDP_INGR_PDISP */ -#define ESF_DZ_C2RIP_BUF_LEN_LBN 240 -#define ESF_DZ_C2RIP_BUF_LEN_WIDTH 16 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_LBN 192 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_LBN 224 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_LBN 192 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2RIP_EV_DISABLE_LBN 191 -#define ESF_DZ_C2RIP_EV_DISABLE_WIDTH 1 -#define ESF_DZ_C2RIP_EV_SOFT_LBN 188 -#define ESF_DZ_C2RIP_EV_SOFT_WIDTH 3 -#define ESF_DZ_C2RIP_EV_DESC_PTR_LBN 176 -#define ESF_DZ_C2RIP_EV_DESC_PTR_WIDTH 12 -#define ESF_DZ_C2RIP_EV_ARG1_LBN 160 -#define ESF_DZ_C2RIP_EV_ARG1_WIDTH 16 -#define ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157 -#define ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_C2RIP_BIU_ARGS_LBN 144 -#define ESF_DZ_C2RIP_BIU_ARGS_WIDTH 13 -#define ESF_DZ_C2RIP_EV_QID_LBN 133 -#define ESF_DZ_C2RIP_EV_QID_WIDTH 11 -#define ESF_DZ_C2RIP_EV_QLABEL_LBN 128 -#define ESF_DZ_C2RIP_EV_QLABEL_WIDTH 5 -#define ESF_DZ_C2RIP_PEDIT_DELTA_LBN 104 -#define ESF_DZ_C2RIP_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_C2RIP_PYLOAD_OFST_LBN 96 -#define ESF_DZ_C2RIP_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_C2RIP_L4_HDR_OFST_LBN 88 -#define ESF_DZ_C2RIP_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2RIP_L3_HDR_OFST_LBN 80 -#define ESF_DZ_C2RIP_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2RIP_IS_UDP_LBN 69 -#define ESF_DZ_C2RIP_IS_UDP_WIDTH 1 -#define ESF_DZ_C2RIP_IS_TCP_LBN 68 -#define ESF_DZ_C2RIP_IS_TCP_WIDTH 1 -#define ESF_DZ_C2RIP_IS_IPV6_LBN 67 -#define ESF_DZ_C2RIP_IS_IPV6_WIDTH 1 -#define ESF_DZ_C2RIP_IS_IPV4_LBN 66 -#define ESF_DZ_C2RIP_IS_IPV4_WIDTH 1 -#define ESF_DZ_C2RIP_IS_FCOE_LBN 65 -#define ESF_DZ_C2RIP_IS_FCOE_WIDTH 1 -#define ESF_DZ_C2RIP_PARSE_INCOMP_LBN 64 -#define ESF_DZ_C2RIP_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_C2RIP_FINFO_WRD3_LBN 48 -#define ESF_DZ_C2RIP_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_C2RIP_FINFO_WRD2_LBN 32 -#define ESF_DZ_C2RIP_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_C2RIP_FINFO_WRD1_LBN 16 -#define ESF_DZ_C2RIP_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_C2RIP_FINFO_SRCDST_LBN 0 -#define ESF_DZ_C2RIP_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_CPU2RXDP_INGR_SOFT */ -#define ESF_DZ_C2RIS_SOFT3_LBN 48 -#define ESF_DZ_C2RIS_SOFT3_WIDTH 16 -#define ESF_DZ_C2RIS_SOFT2_LBN 32 -#define ESF_DZ_C2RIS_SOFT2_WIDTH 16 -#define ESF_DZ_C2RIS_SOFT1_LBN 16 -#define ESF_DZ_C2RIS_SOFT1_WIDTH 16 -#define ESF_DZ_C2RIS_SOFT0_LBN 0 -#define ESF_DZ_C2RIS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_CPU2SMC_BUFLKUP */ -#define ESF_DZ_C2SB_PAGE_ID_LBN 16 -#define ESF_DZ_C2SB_PAGE_ID_WIDTH 18 -#define ESF_DZ_C2SB_EXP_PAGE_ID_LBN 0 -#define ESF_DZ_C2SB_EXP_PAGE_ID_WIDTH 12 - - -/* ES_FF_UMSG_CPU2SMC_DESCOP */ -#define ESF_DZ_C2SD_LEN_LBN 112 -#define ESF_DZ_C2SD_LEN_WIDTH 14 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2SD_OFFSET_LBN 80 -#define ESF_DZ_C2SD_OFFSET_WIDTH 8 -#define ESF_DZ_C2SD_QID_LBN 32 -#define ESF_DZ_C2SD_QID_WIDTH 11 -#define ESF_DZ_C2SD_CONT_LBN 16 -#define ESF_DZ_C2SD_CONT_WIDTH 1 -#define ESF_DZ_C2SD_TYPE_LBN 0 -#define ESF_DZ_C2SD_TYPE_WIDTH 1 - - -/* ES_FF_UMSG_CPU2SMC_GPOP */ -#define ESF_DZ_C2SG_DATA_DW0_LBN 64 -#define ESF_DZ_C2SG_DATA_DW0_WIDTH 32 -#define ESF_DZ_C2SG_DATA_DW1_LBN 96 -#define ESF_DZ_C2SG_DATA_DW1_WIDTH 32 -#define ESF_DZ_C2SG_DATA_LBN 64 -#define ESF_DZ_C2SG_DATA_WIDTH 64 -#define ESF_DZ_C2SG_SOFT_LBN 48 -#define ESF_DZ_C2SG_SOFT_WIDTH 4 -#define ESF_DZ_C2SG_REFLECT_LBN 32 -#define ESF_DZ_C2SG_REFLECT_WIDTH 1 -#define ESF_DZ_C2SG_ADDR_LBN 0 -#define ESF_DZ_C2SG_ADDR_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_DMA_BUFREQ */ -#define ESF_DZ_C2TDB_BUF_LEN_LBN 176 -#define ESF_DZ_C2TDB_BUF_LEN_WIDTH 16 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_LBN 128 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_LBN 160 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_LBN 128 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2TDB_SOFT_LBN 112 -#define ESF_DZ_C2TDB_SOFT_WIDTH 14 -#define ESF_DZ_C2TDB_DESC_IDX_LBN 96 -#define ESF_DZ_C2TDB_DESC_IDX_WIDTH 16 -#define ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93 -#define ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_C2TDB_BIU_ARGS_LBN 80 -#define ESF_DZ_C2TDB_BIU_ARGS_WIDTH 13 -#define ESF_DZ_C2TDB_CONT_LBN 64 -#define ESF_DZ_C2TDB_CONT_WIDTH 1 -#define ESF_DZ_C2TDB_FINFO_WRD3_LBN 48 -#define ESF_DZ_C2TDB_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_C2TDB_FINFO_WRD2_LBN 32 -#define ESF_DZ_C2TDB_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_C2TDB_FINFO_WRD1_LBN 16 -#define ESF_DZ_C2TDB_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_C2TDB_FINFO_SRCDST_LBN 0 -#define ESF_DZ_C2TDB_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_DMA_PKTABORT */ -#define ESF_DZ_C2TDP_SOFT_LBN 48 -#define ESF_DZ_C2TDP_SOFT_WIDTH 14 -#define ESF_DZ_C2TDP_DESC_IDX_LBN 32 -#define ESF_DZ_C2TDP_DESC_IDX_WIDTH 16 -#define ESF_DZ_C2TDP_BIU_ARGS_LBN 16 -#define ESF_DZ_C2TDP_BIU_ARGS_WIDTH 14 - - -/* ES_FF_UMSG_CPU2TXDP_DMA_SOFT */ -#define ESF_DZ_C2TDS_SOFT3_LBN 48 -#define ESF_DZ_C2TDS_SOFT3_WIDTH 16 -#define ESF_DZ_C2TDS_SOFT2_LBN 32 -#define ESF_DZ_C2TDS_SOFT2_WIDTH 16 -#define ESF_DZ_C2TDS_SOFT1_LBN 16 -#define ESF_DZ_C2TDS_SOFT1_WIDTH 16 -#define ESF_DZ_C2TDS_SOFT0_LBN 0 -#define ESF_DZ_C2TDS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_EGR */ -#define ESF_DZ_C2TE_RMON_SOFT_LBN 240 -#define ESF_DZ_C2TE_RMON_SOFT_WIDTH 1 -#define ESF_DZ_C2TE_VLAN_PRIO_LBN 224 -#define ESF_DZ_C2TE_VLAN_PRIO_WIDTH 3 -#define ESF_DZ_C2TE_VLAN_LBN 208 -#define ESF_DZ_C2TE_VLAN_WIDTH 1 -#define ESF_DZ_C2TE_QID_LBN 192 -#define ESF_DZ_C2TE_QID_WIDTH 11 -#define ESF_DZ_C2TE_PEDIT_DELTA_LBN 168 -#define ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_C2TE_PYLOAD_OFST_LBN 160 -#define ESF_DZ_C2TE_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_C2TE_L4_HDR_OFST_LBN 152 -#define ESF_DZ_C2TE_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2TE_L3_HDR_OFST_LBN 144 -#define ESF_DZ_C2TE_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2TE_IS_UDP_LBN 133 -#define ESF_DZ_C2TE_IS_UDP_WIDTH 1 -#define ESF_DZ_C2TE_IS_TCP_LBN 132 -#define ESF_DZ_C2TE_IS_TCP_WIDTH 1 -#define ESF_DZ_C2TE_IS_IPV6_LBN 131 -#define ESF_DZ_C2TE_IS_IPV6_WIDTH 1 -#define ESF_DZ_C2TE_IS_IPV4_LBN 130 -#define ESF_DZ_C2TE_IS_IPV4_WIDTH 1 -#define ESF_DZ_C2TE_IS_FCOE_LBN 129 -#define ESF_DZ_C2TE_IS_FCOE_WIDTH 1 -#define ESF_DZ_C2TE_PARSE_INCOMP_LBN 128 -#define ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 98 -#define ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 -#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 -#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 -#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 -#define ESF_DZ_C2TE_PKT_LEN_LBN 64 -#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_WRD3_LBN 48 -#define ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_WRD2_LBN 32 -#define ESF_DZ_C2TE_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_WRD1_LBN 16 -#define ESF_DZ_C2TE_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_SRCDST_LBN 0 -#define ESF_DZ_C2TE_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_EGR_SOFT */ -#define ESF_DZ_C2TES_SOFT3_LBN 48 -#define ESF_DZ_C2TES_SOFT3_WIDTH 16 -#define ESF_DZ_C2TES_SOFT2_LBN 32 -#define ESF_DZ_C2TES_SOFT2_WIDTH 16 -#define ESF_DZ_C2TES_SOFT1_LBN 16 -#define ESF_DZ_C2TES_SOFT1_WIDTH 16 -#define ESF_DZ_C2TES_SOFT0_LBN 0 -#define ESF_DZ_C2TES_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_DL2CPU_DESC_FETCH */ -#define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_LBN 64 -#define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_D2CDF_FAIL_LBN 48 -#define ESF_DZ_D2CDF_FAIL_WIDTH 1 -#define ESF_DZ_D2CDF_QID_LBN 32 -#define ESF_DZ_D2CDF_QID_WIDTH 11 -#define ESF_DZ_D2CDF_NUM_DESC_LBN 16 -#define ESF_DZ_D2CDF_NUM_DESC_WIDTH 7 -#define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_LBN 0 -#define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_WIDTH 12 - - -/* ES_FF_UMSG_DL2CPU_GPRD */ -#define ESF_DZ_D2CG_BIU_ARGS_LBN 0 -#define ESF_DZ_D2CG_BIU_ARGS_WIDTH 14 - - -/* ES_FF_UMSG_DPCPU_PACER_TXQ_D_R_I_REQ */ -#define ESF_DZ_FRM_LEN_LBN 16 -#define ESF_DZ_FRM_LEN_WIDTH 15 -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */ -#define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */ -#define ESF_DZ_DUE_TIME_LBN 80 -#define ESF_DZ_DUE_TIME_WIDTH 16 -#define ESF_DZ_LAST_FILL_TIME_LBN 64 -#define ESF_DZ_LAST_FILL_TIME_WIDTH 16 -#define ESF_DZ_RATE_REC_LBN 48 -#define ESF_DZ_RATE_REC_WIDTH 16 -#define ESF_DZ_RATE_LBN 32 -#define ESF_DZ_RATE_WIDTH 16 -#define ESF_DZ_FILL_LEVEL_LBN 16 -#define ESF_DZ_FILL_LEVEL_WIDTH 16 -#define ESF_DZ_IDLE_LBN 15 -#define ESF_DZ_IDLE_WIDTH 1 -#define ESF_DZ_USED_LBN 14 -#define ESF_DZ_USED_WIDTH 1 -#define ESF_DZ_MAX_FILL_REG_LBN 12 -#define ESF_DZ_MAX_FILL_REG_WIDTH 2 -#define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */ -#define ESF_DZ_RATE_REC_LBN 48 -#define ESF_DZ_RATE_REC_WIDTH 16 -#define ESF_DZ_RATE_LBN 32 -#define ESF_DZ_RATE_WIDTH 16 -#define ESF_DZ_FILL_LEVEL_LBN 16 -#define ESF_DZ_FILL_LEVEL_WIDTH 16 -#define ESF_DZ_IDLE_LBN 15 -#define ESF_DZ_IDLE_WIDTH 1 -#define ESF_DZ_USED_LBN 14 -#define ESF_DZ_USED_WIDTH 1 -#define ESF_DZ_MAX_FILL_REG_LBN 12 -#define ESF_DZ_MAX_FILL_REG_WIDTH 2 -#define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */ -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */ -#define ESF_DZ_MAX_BKT2_LBN 112 -#define ESF_DZ_MAX_BKT2_WIDTH 10 -#define ESF_DZ_MAX_BKT1_LBN 96 -#define ESF_DZ_MAX_BKT1_WIDTH 10 -#define ESF_DZ_MAX_BKT0_LBN 80 -#define ESF_DZ_MAX_BKT0_WIDTH 10 -#define ESF_DZ_MIN_BKT_LBN 64 -#define ESF_DZ_MIN_BKT_WIDTH 10 -#define ESF_DZ_LABEL_LBN 48 -#define ESF_DZ_LABEL_WIDTH 4 -#define ESF_DZ_PQ_FLAGS_LBN 32 -#define ESF_DZ_PQ_FLAGS_WIDTH 3 -#define ESF_DZ_DSBL_LBN 16 -#define ESF_DZ_DSBL_WIDTH 1 -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */ -#define ESF_DZ_MAX_BKT2_LBN 112 -#define ESF_DZ_MAX_BKT2_WIDTH 10 -#define ESF_DZ_MAX_BKT1_LBN 96 -#define ESF_DZ_MAX_BKT1_WIDTH 10 -#define ESF_DZ_MAX_BKT0_LBN 80 -#define ESF_DZ_MAX_BKT0_WIDTH 10 -#define ESF_DZ_MIN_BKT_LBN 64 -#define ESF_DZ_MIN_BKT_WIDTH 10 -#define ESF_DZ_LABEL_LBN 48 -#define ESF_DZ_LABEL_WIDTH 4 -#define ESF_DZ_PQ_FLAGS_LBN 32 -#define ESF_DZ_PQ_FLAGS_WIDTH 3 -#define ESF_DZ_DSBL_LBN 16 -#define ESF_DZ_DSBL_WIDTH 1 -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PE */ -#define ESF_DZ_PE_PKT_OFST_LBN 47 -#define ESF_DZ_PE_PKT_OFST_WIDTH 17 -#define ESF_DZ_PE_PEDIT_DELTA_LBN 40 -#define ESF_DZ_PE_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_PE_PYLOAD_OFST_LBN 32 -#define ESF_DZ_PE_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_PE_L4_HDR_OFST_LBN 24 -#define ESF_DZ_PE_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_PE_L3_HDR_OFST_LBN 16 -#define ESF_DZ_PE_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_PE_HAVE_UDP_HDR_LBN 5 -#define ESF_DZ_PE_HAVE_UDP_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_TCP_HDR_LBN 4 -#define ESF_DZ_PE_HAVE_TCP_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_IPV6_HDR_LBN 3 -#define ESF_DZ_PE_HAVE_IPV6_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_IPV4_HDR_LBN 2 -#define ESF_DZ_PE_HAVE_IPV4_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_FCOE_LBN 1 -#define ESF_DZ_PE_HAVE_FCOE_WIDTH 1 -#define ESF_DZ_PE_PARSE_INCOMP_LBN 0 -#define ESF_DZ_PE_PARSE_INCOMP_WIDTH 1 - - -/* ES_FF_UMSG_RXDP_EGR2CPU_SOFT */ -#define ESF_DZ_RE2CS_SOFT3_LBN 48 -#define ESF_DZ_RE2CS_SOFT3_WIDTH 16 -#define ESF_DZ_RE2CS_SOFT2_LBN 32 -#define ESF_DZ_RE2CS_SOFT2_WIDTH 16 -#define ESF_DZ_RE2CS_SOFT1_LBN 16 -#define ESF_DZ_RE2CS_SOFT1_WIDTH 16 -#define ESF_DZ_RE2CS_SOFT0_LBN 0 -#define ESF_DZ_RE2CS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_RXDP_INGR2CPU */ -#define ESF_DZ_RI2C_QUEUE_ID_LBN 224 -#define ESF_DZ_RI2C_QUEUE_ID_WIDTH 11 -#define ESF_DZ_RI2C_LEN_LBN 208 -#define ESF_DZ_RI2C_LEN_WIDTH 16 -#define ESF_DZ_RI2C_L4_CLASS_LBN 205 -#define ESF_DZ_RI2C_L4_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_L3_CLASS_LBN 202 -#define ESF_DZ_RI2C_L3_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 199 -#define ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 196 -#define ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_MAC_CLASS_LBN 195 -#define ESF_DZ_RI2C_MAC_CLASS_WIDTH 1 -#define ESF_DZ_RI2C_PKT_OFST_LBN 176 -#define ESF_DZ_RI2C_PKT_OFST_WIDTH 16 -#define ESF_DZ_RI2C_PEDIT_DELTA_LBN 168 -#define ESF_DZ_RI2C_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_RI2C_PYLOAD_OFST_LBN 160 -#define ESF_DZ_RI2C_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_RI2C_L4_HDR_OFST_LBN 152 -#define ESF_DZ_RI2C_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_RI2C_L3_HDR_OFST_LBN 144 -#define ESF_DZ_RI2C_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_RI2C_HAVE_UDP_HDR_LBN 133 -#define ESF_DZ_RI2C_HAVE_UDP_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_TCP_HDR_LBN 132 -#define ESF_DZ_RI2C_HAVE_TCP_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_IPV6_HDR_LBN 131 -#define ESF_DZ_RI2C_HAVE_IPV6_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_IPV4_HDR_LBN 130 -#define ESF_DZ_RI2C_HAVE_IPV4_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_FCOE_LBN 129 -#define ESF_DZ_RI2C_HAVE_FCOE_WIDTH 1 -#define ESF_DZ_RI2C_PARSE_INCOMP_LBN 128 -#define ESF_DZ_RI2C_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_RI2C_EFINFO_WRD3_LBN 112 -#define ESF_DZ_RI2C_EFINFO_WRD3_WIDTH 16 -#define ESF_DZ_RI2C_EFINFO_WRD2_LBN 96 -#define ESF_DZ_RI2C_EFINFO_WRD2_WIDTH 16 -#define ESF_DZ_RI2C_EFINFO_WRD1_LBN 80 -#define ESF_DZ_RI2C_EFINFO_WRD1_WIDTH 16 -#define ESF_DZ_RI2C_EFINFO_WRD0_LBN 64 -#define ESF_DZ_RI2C_EFINFO_WRD0_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_WRD3_LBN 48 -#define ESF_DZ_RI2C_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_WRD2_LBN 32 -#define ESF_DZ_RI2C_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_WRD1_LBN 16 -#define ESF_DZ_RI2C_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_SRCDST_LBN 0 -#define ESF_DZ_RI2C_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_SMC2CPU_BUFLKUP */ -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_LBN 0 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_WIDTH 32 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_LBN 32 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_WIDTH 16 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_LBN 0 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_WIDTH 48 -#define ESF_DZ_S2CB_FAIL_LBN 32 -#define ESF_DZ_S2CB_FAIL_WIDTH 1 - - -/* ES_FF_UMSG_SMC2CPU_DESCRD */ -#define ESF_DZ_S2CD_BUF_LEN_LBN 112 -#define ESF_DZ_S2CD_BUF_LEN_WIDTH 14 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_S2CD_CONT_LBN 16 -#define ESF_DZ_S2CD_CONT_WIDTH 1 -#define ESF_DZ_S2CD_TYPE_LBN 0 -#define ESF_DZ_S2CD_TYPE_WIDTH 1 - - -/* ES_FF_UMSG_SMC2CPU_GPRD */ -#define ESF_DZ_S2CG_DATA_DW0_LBN 64 -#define ESF_DZ_S2CG_DATA_DW0_WIDTH 32 -#define ESF_DZ_S2CG_DATA_DW1_LBN 96 -#define ESF_DZ_S2CG_DATA_DW1_WIDTH 32 -#define ESF_DZ_S2CG_DATA_LBN 64 -#define ESF_DZ_S2CG_DATA_WIDTH 64 -#define ESF_DZ_S2CG_SOFT_LBN 48 -#define ESF_DZ_S2CG_SOFT_WIDTH 4 -#define ESF_DZ_S2CG_FAIL_LBN 32 -#define ESF_DZ_S2CG_FAIL_WIDTH 1 - - -/* ES_FF_UMSG_TXDP_DMA2CPU_PKTRDY */ -#define ESF_DZ_TD2CP_L4_CLASS_LBN 250 -#define ESF_DZ_TD2CP_L4_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_L3_CLASS_LBN 247 -#define ESF_DZ_TD2CP_L3_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_ETHTAG_CLASS_LBN 244 -#define ESF_DZ_TD2CP_ETHTAG_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_ETHBASE_CLASS_LBN 241 -#define ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_MAC_CLASS_LBN 240 -#define ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1 -#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_LBN 239 -#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_WIDTH 1 -#define ESF_DZ_TD2CP_PKT_ABORT_LBN 238 -#define ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1 -#define ESF_DZ_TD2CP_SOFT_LBN 224 -#define ESF_DZ_TD2CP_SOFT_WIDTH 14 -#define ESF_DZ_TD2CP_DESC_IDX_LBN 208 -#define ESF_DZ_TD2CP_DESC_IDX_WIDTH 16 -#define ESF_DZ_TD2CP_PKT_LEN_LBN 192 -#define ESF_DZ_TD2CP_PKT_LEN_WIDTH 16 -#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_LBN 176 -#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_WIDTH 7 -#define ESF_DZ_TD2CP_PEDIT_DELTA_LBN 168 -#define ESF_DZ_TD2CP_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_TD2CP_PYLOAD_OFST_LBN 160 -#define ESF_DZ_TD2CP_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_TD2CP_L4_HDR_OFST_LBN 152 -#define ESF_DZ_TD2CP_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_TD2CP_L3_HDR_OFST_LBN 144 -#define ESF_DZ_TD2CP_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_TD2CP_IS_UDP_LBN 133 -#define ESF_DZ_TD2CP_IS_UDP_WIDTH 1 -#define ESF_DZ_TD2CP_IS_TCP_LBN 132 -#define ESF_DZ_TD2CP_IS_TCP_WIDTH 1 -#define ESF_DZ_TD2CP_IS_IPV6_LBN 131 -#define ESF_DZ_TD2CP_IS_IPV6_WIDTH 1 -#define ESF_DZ_TD2CP_IS_IPV4_LBN 130 -#define ESF_DZ_TD2CP_IS_IPV4_WIDTH 1 -#define ESF_DZ_TD2CP_IS_FCOE_LBN 129 -#define ESF_DZ_TD2CP_IS_FCOE_WIDTH 1 -#define ESF_DZ_TD2CP_PARSE_INCOMP_LBN 128 -#define ESF_DZ_TD2CP_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_TD2CP_EFINFO_WRD3_LBN 112 -#define ESF_DZ_TD2CP_EFINFO_WRD3_WIDTH 16 -#define ESF_DZ_TD2CP_EFINFO_WRD2_LBN 96 -#define ESF_DZ_TD2CP_EFINFO_WRD2_WIDTH 16 -#define ESF_DZ_TD2CP_EFINFO_WRD1_LBN 80 -#define ESF_DZ_TD2CP_EFINFO_WRD1_WIDTH 16 -#define ESF_DZ_TD2CP_EFINFO_WRD0_LBN 64 -#define ESF_DZ_TD2CP_EFINFO_WRD0_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_WRD3_LBN 48 -#define ESF_DZ_TD2CP_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_WRD2_LBN 32 -#define ESF_DZ_TD2CP_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_WRD1_LBN 16 -#define ESF_DZ_TD2CP_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_SRCDST_LBN 0 -#define ESF_DZ_TD2CP_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_TXDP_DMA2CPU_SOFT */ -#define ESF_DZ_TD2CS_SOFT3_LBN 48 -#define ESF_DZ_TD2CS_SOFT3_WIDTH 16 -#define ESF_DZ_TD2CS_SOFT2_LBN 32 -#define ESF_DZ_TD2CS_SOFT2_WIDTH 16 -#define ESF_DZ_TD2CS_SOFT1_LBN 16 -#define ESF_DZ_TD2CS_SOFT1_WIDTH 16 -#define ESF_DZ_TD2CS_SOFT0_LBN 0 -#define ESF_DZ_TD2CS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_TXDP_EGR2CPU_SOFT */ -#define ESF_DZ_TE2CS_SOFT3_LBN 48 -#define ESF_DZ_TE2CS_SOFT3_WIDTH 16 -#define ESF_DZ_TE2CS_SOFT2_LBN 32 -#define ESF_DZ_TE2CS_SOFT2_WIDTH 16 -#define ESF_DZ_TE2CS_SOFT1_LBN 16 -#define ESF_DZ_TE2CS_SOFT1_WIDTH 16 -#define ESF_DZ_TE2CS_SOFT0_LBN 0 -#define ESF_DZ_TE2CS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_VICTL2CPU */ -#define ESF_DZ_V2C_DESC_WORD3_LBN 112 -#define ESF_DZ_V2C_DESC_WORD3_WIDTH 17 -#define ESF_DZ_V2C_DESC_WORD2_LBN 96 -#define ESF_DZ_V2C_DESC_WORD2_WIDTH 16 -#define ESF_DZ_V2C_DESC_WORD1_LBN 80 -#define ESF_DZ_V2C_DESC_WORD1_WIDTH 16 -#define ESF_DZ_V2C_DESC_WORD0_LBN 64 -#define ESF_DZ_V2C_DESC_WORD0_WIDTH 16 -#define ESF_DZ_V2C_NEW_DSCR_WPTR_LBN 32 -#define ESF_DZ_V2C_NEW_DSCR_WPTR_WIDTH 12 -#define ESF_DZ_V2C_DESC_PUSH_LBN 16 -#define ESF_DZ_V2C_DESC_PUSH_WIDTH 1 - - -/* ES_LUE_DB_MATCH_ENTRY */ -#define ESF_DZ_LUE_DSCRMNTR_LBN 140 -#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 -#define ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44 -#define ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32 -#define ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76 -#define ESF_DZ_LUE_MATCH_VAL_DW1_WIDTH 32 -#define ESF_DZ_LUE_MATCH_VAL_DW2_LBN 108 -#define ESF_DZ_LUE_MATCH_VAL_DW2_WIDTH 32 -#define ESF_DZ_LUE_MATCH_VAL_LBN 44 -#define ESF_DZ_LUE_MATCH_VAL_WIDTH 96 -#define ESF_DZ_LUE_ME_SOFT_LBN 35 -#define ESF_DZ_LUE_ME_SOFT_WIDTH 9 -#define ESF_DZ_LUE_TX_MCAST_LBN 33 -#define ESF_DZ_LUE_TX_MCAST_WIDTH 2 -#define ESF_DZ_LUE_TX_DOMAIN_LBN 25 -#define ESF_DZ_LUE_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_LUE_RX_MCAST_LBN 24 -#define ESF_DZ_LUE_RX_MCAST_WIDTH 1 -#define ESE_DZ_LUE_MULTI 1 -#define ESE_DZ_LUE_SINGLE 0 -#define ESF_DZ_LUE_RCPNTR_LBN 0 -#define ESF_DZ_LUE_RCPNTR_WIDTH 24 - - -/* ES_LUE_DB_NONMATCH_ENTRY */ -#define ESF_DZ_LUE_DSCRMNTR_LBN 140 -#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 -#define ESF_DZ_LUE_TERMINAL_LBN 139 -#define ESF_DZ_LUE_TERMINAL_WIDTH 1 -#define ESF_DZ_LUE_LAST_LBN 138 -#define ESF_DZ_LUE_LAST_WIDTH 1 -#define ESF_DZ_LUE_NE_SOFT_LBN 137 -#define ESF_DZ_LUE_NE_SOFT_WIDTH 1 -#define ESF_DZ_LUE_RCPNTR_NUM_LBN 134 -#define ESF_DZ_LUE_RCPNTR_NUM_WIDTH 3 -#define ESF_DZ_LUE_RCPNTR0_LBN 110 -#define ESF_DZ_LUE_RCPNTR0_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR1_LBN 86 -#define ESF_DZ_LUE_RCPNTR1_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR2_LBN 62 -#define ESF_DZ_LUE_RCPNTR2_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR3_LBN 38 -#define ESF_DZ_LUE_RCPNTR3_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR4_LBN 14 -#define ESF_DZ_LUE_RCPNTR4_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR_NE_PTR_LBN 0 -#define ESF_DZ_LUE_RCPNTR_NE_PTR_WIDTH 14 - - -/* ES_LUE_MC_DIRECT_REQUEST_MSG */ -#define ESF_DZ_MC2L_DR_PAD_DW0_LBN 22 -#define ESF_DZ_MC2L_DR_PAD_DW0_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW1_LBN 54 -#define ESF_DZ_MC2L_DR_PAD_DW1_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW2_LBN 86 -#define ESF_DZ_MC2L_DR_PAD_DW2_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW3_LBN 118 -#define ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW4_LBN 150 -#define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 18 -#define ESF_DZ_MC2L_DR_PAD_LBN 22 -#define ESF_DZ_MC2L_DR_PAD_WIDTH 146 -#define ESF_DZ_MC2L_DR_ADDR_LBN 8 -#define ESF_DZ_MC2L_DR_ADDR_WIDTH 14 -#define ESF_DZ_MC2L_DR_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_DR_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_DR_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_DR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_DR_OP_LBN 0 -#define ESF_DZ_MC2L_DR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_DIRECT_RESPONSE_MSG */ -#define ESF_DZ_L2MC_DR_PAD_LBN 146 -#define ESF_DZ_L2MC_DR_PAD_WIDTH 8 -#define ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132 -#define ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14 -#define ESF_DZ_L2MC_DR_RCPNT4_LBN 108 -#define ESF_DZ_L2MC_DR_RCPNT4_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT3_LBN 84 -#define ESF_DZ_L2MC_DR_RCPNT3_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT2_LBN 60 -#define ESF_DZ_L2MC_DR_RCPNT2_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT1_LBN 36 -#define ESF_DZ_L2MC_DR_RCPNT1_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT0_LBN 12 -#define ESF_DZ_L2MC_DR_RCPNT0_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT_NUM_LBN 9 -#define ESF_DZ_L2MC_DR_RCPNT_NUM_WIDTH 3 -#define ESF_DZ_L2MC_DR_LAST_LBN 8 -#define ESF_DZ_L2MC_DR_LAST_WIDTH 1 -#define ESF_DZ_L2MC_DR_THREAD_ID_LBN 5 -#define ESF_DZ_L2MC_DR_THREAD_ID_WIDTH 3 -#define ESF_DZ_L2MC_DR_CLIENT_ID_LBN 2 -#define ESF_DZ_L2MC_DR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_L2MC_DR_OP_LBN 0 -#define ESF_DZ_L2MC_DR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_GP_RD_REQUEST_MSG */ -#define ESF_DZ_MC2L_GPR_PAD_DW0_LBN 22 -#define ESF_DZ_MC2L_GPR_PAD_DW0_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW1_LBN 54 -#define ESF_DZ_MC2L_GPR_PAD_DW1_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW2_LBN 86 -#define ESF_DZ_MC2L_GPR_PAD_DW2_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118 -#define ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150 -#define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 18 -#define ESF_DZ_MC2L_GPR_PAD_LBN 22 -#define ESF_DZ_MC2L_GPR_PAD_WIDTH 146 -#define ESF_DZ_MC2L_GPR_ADDR_LBN 8 -#define ESF_DZ_MC2L_GPR_ADDR_WIDTH 14 -#define ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_GPR_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPR_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_GPR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPR_OP_LBN 0 -#define ESF_DZ_MC2L_GPR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_GP_RD_RESPONSE_MSG */ -#define ESF_DZ_L2MC_GPR_DATA_DW0_LBN 8 -#define ESF_DZ_L2MC_GPR_DATA_DW0_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW1_LBN 40 -#define ESF_DZ_L2MC_GPR_DATA_DW1_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW2_LBN 72 -#define ESF_DZ_L2MC_GPR_DATA_DW2_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104 -#define ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136 -#define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 18 -#define ESF_DZ_L2MC_GPR_DATA_LBN 8 -#define ESF_DZ_L2MC_GPR_DATA_WIDTH 146 -#define ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5 -#define ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3 -#define ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2 -#define ESF_DZ_L2MC_GPR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_L2MC_GPR_OP_LBN 0 -#define ESF_DZ_L2MC_GPR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_GP_WR_REQUEST_MSG */ -#define ESF_DZ_MC2L_GPW_DATA_DW0_LBN 22 -#define ESF_DZ_MC2L_GPW_DATA_DW0_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW1_LBN 54 -#define ESF_DZ_MC2L_GPW_DATA_DW1_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW2_LBN 86 -#define ESF_DZ_MC2L_GPW_DATA_DW2_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118 -#define ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150 -#define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 18 -#define ESF_DZ_MC2L_GPW_DATA_LBN 22 -#define ESF_DZ_MC2L_GPW_DATA_WIDTH 146 -#define ESF_DZ_MC2L_GPW_ADDR_LBN 8 -#define ESF_DZ_MC2L_GPW_ADDR_WIDTH 14 -#define ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_GPW_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPW_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_GPW_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPW_OP_LBN 0 -#define ESF_DZ_MC2L_GPW_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_MATCH_REQUEST_MSG */ -#define ESF_DZ_MC2L_MR_PAD_LBN 137 -#define ESF_DZ_MC2L_MR_PAD_WIDTH 31 -#define ESF_DZ_MC2L_MR_HASH2_LBN 124 -#define ESF_DZ_MC2L_MR_HASH2_WIDTH 13 -#define ESF_DZ_MC2L_MR_HASH1_LBN 110 -#define ESF_DZ_MC2L_MR_HASH1_WIDTH 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 46 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 78 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96 -#define ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8 -#define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 6 -#define ESF_DZ_MC2L_MR_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_MR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_MR_OP_LBN 0 -#define ESF_DZ_MC2L_MR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_MATCH_RESPONSE_MSG */ -#define ESF_DZ_L2MC_MR_PAD_DW0_LBN 53 -#define ESF_DZ_L2MC_MR_PAD_DW0_WIDTH 32 -#define ESF_DZ_L2MC_MR_PAD_DW1_LBN 85 -#define ESF_DZ_L2MC_MR_PAD_DW1_WIDTH 32 -#define ESF_DZ_L2MC_MR_PAD_DW2_LBN 117 -#define ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32 -#define ESF_DZ_L2MC_MR_PAD_DW3_LBN 149 -#define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 5 -#define ESF_DZ_L2MC_MR_PAD_LBN 53 -#define ESF_DZ_L2MC_MR_PAD_WIDTH 101 -#define ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29 -#define ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24 -#define ESF_DZ_L2MC_MR_RX_MCAST_LBN 28 -#define ESF_DZ_L2MC_MR_RX_MCAST_WIDTH 1 -#define ESF_DZ_L2MC_MR_TX_DOMAIN_LBN 20 -#define ESF_DZ_L2MC_MR_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_L2MC_MR_TX_MCAST_LBN 18 -#define ESF_DZ_L2MC_MR_TX_MCAST_WIDTH 2 -#define ESF_DZ_L2MC_MR_SOFT_LBN 9 -#define ESF_DZ_L2MC_MR_SOFT_WIDTH 9 -#define ESF_DZ_L2MC_MR_MATCH_LBN 8 -#define ESF_DZ_L2MC_MR_MATCH_WIDTH 1 -#define ESF_DZ_L2MC_MR_THREAD_ID_LBN 5 -#define ESF_DZ_L2MC_MR_THREAD_ID_WIDTH 3 -#define ESF_DZ_L2MC_MR_CLIENT_ID_LBN 2 -#define ESF_DZ_L2MC_MR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_L2MC_MR_OP_LBN 0 -#define ESF_DZ_L2MC_MR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_BASE_REQ */ -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_LBN 8 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_LBN 40 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_LBN 72 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 160 -#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_REQ_BASE_OP_LBN 0 -#define ESF_DZ_LUE_HW_REQ_BASE_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_BASE_RESP */ -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_LBN 8 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_LBN 40 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_LBN 72 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 18 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 146 -#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_RSP_BASE_OP_LBN 0 *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***