From owner-svn-src-all@FreeBSD.ORG Sat Dec 6 01:01:18 2008 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2B7081065670; Sat, 6 Dec 2008 01:01:18 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 18A128FC13; Sat, 6 Dec 2008 01:01:18 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id mB611HgZ078190; Sat, 6 Dec 2008 01:01:17 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id mB611HqV078189; Sat, 6 Dec 2008 01:01:17 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <200812060101.mB611HqV078189@svn.freebsd.org> From: Pyun YongHyeon Date: Sat, 6 Dec 2008 01:01:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r185659 - in stable/7/sys: . dev/ale X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Dec 2008 01:01:18 -0000 Author: yongari Date: Sat Dec 6 01:01:17 2008 New Revision: 185659 URL: http://svn.freebsd.org/changeset/base/185659 Log: MFC r185576: Add some PHY magic to enable PHY hibernation and 1000baseT/10baseT power adjustment. This change is required to guarantee correct operation on certain switches. MFC r185577: AR8113 also need to set DMA read burst value. This should fix occasional DMA read error seen on AR8113. Approved by: re (kensmith) Modified: stable/7/sys/ (props changed) stable/7/sys/dev/ale/if_ale.c Modified: stable/7/sys/dev/ale/if_ale.c ============================================================================== --- stable/7/sys/dev/ale/if_ale.c Fri Dec 5 22:36:49 2008 (r185658) +++ stable/7/sys/dev/ale/if_ale.c Sat Dec 6 01:01:17 2008 (r185659) @@ -385,6 +385,39 @@ ale_phy_reset(struct ale_softc *sc) GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); DELAY(1000); + +#define ATPHY_DBG_ADDR 0x1D +#define ATPHY_DBG_DATA 0x1E + + /* Enable hibernation mode. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x0B); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0xBC00); + /* Set Class A/B for all modes. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x00); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0x02EF); + /* Enable 10BT power saving. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x12); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_DATA, 0x4C04); + /* Adjust 1000T power. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x04); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x8BBB); + /* 10BT center tap voltage. */ + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x05); + ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, + ATPHY_DBG_ADDR, 0x2C46); + +#undef ATPHY_DBG_ADDR +#undef ATPHY_DBG_DATA + DELAY(1000); } static int @@ -2753,10 +2786,8 @@ ale_init_locked(struct ale_softc *sc) TX_JUMBO_THRESH_UNIT_SHIFT); } /* Configure TxQ. */ - reg = 0; - if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) - reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) - << TXQ_CFG_TX_FIFO_BURST_SHIFT; + reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) + << TXQ_CFG_TX_FIFO_BURST_SHIFT; reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & TXQ_CFG_TPD_BURST_MASK; CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);