From owner-svn-src-head@freebsd.org Sat Apr 27 00:53:42 2019 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id A98EA15A2EB1; Sat, 27 Apr 2019 00:53:42 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4F34E8E6A6; Sat, 27 Apr 2019 00:53:42 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 259EF1BA46; Sat, 27 Apr 2019 00:53:42 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x3R0rgg3056132; Sat, 27 Apr 2019 00:53:42 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x3R0rf9u056130; Sat, 27 Apr 2019 00:53:41 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <201904270053.x3R0rf9u056130@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Sat, 27 Apr 2019 00:53:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r346771 - head/sys/powerpc/powerpc X-SVN-Group: head X-SVN-Commit-Author: jhibbits X-SVN-Commit-Paths: head/sys/powerpc/powerpc X-SVN-Commit-Revision: 346771 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 4F34E8E6A6 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.94 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.996,0]; NEURAL_HAM_SHORT(-0.94)[-0.939,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 27 Apr 2019 00:53:43 -0000 Author: jhibbits Date: Sat Apr 27 00:53:41 2019 New Revision: 346771 URL: https://svnweb.freebsd.org/changeset/base/346771 Log: powerpc: micro-optimize cpu_switch() Since the non-volatile registers are restored at the end of cpu_switchin (of the new thread) they're free for us to use for our own purposes. Load the PCB_FLAGS into a non-volatile register so it's preserved across the C function calls that manage FPU and altivec state. This removes 4 loads from each file. Might be a trivial performance improvement (~12 clock cycles per context switch). MFC after: 3 weeks Modified: head/sys/powerpc/powerpc/swtch32.S head/sys/powerpc/powerpc/swtch64.S Modified: head/sys/powerpc/powerpc/swtch32.S ============================================================================== --- head/sys/powerpc/powerpc/swtch32.S Fri Apr 26 22:18:22 2019 (r346770) +++ head/sys/powerpc/powerpc/swtch32.S Sat Apr 27 00:53:41 2019 (r346771) @@ -98,17 +98,16 @@ ENTRY(cpu_switch) mr %r16,%r5 /* and the new lock */ mr %r17,%r6 /* and the PCB */ - lwz %r7,PCB_FLAGS(%r17) + lwz %r18,PCB_FLAGS(%r17) /* Save FPU context if needed */ - andi. %r7, %r7, PCB_FPU + andi. %r7, %r18, PCB_FPU beq .L1 bl save_fpu .L1: mr %r3,%r14 /* restore old thread ptr */ - lwz %r7,PCB_FLAGS(%r17) /* Save Altivec context if needed */ - andi. %r7, %r7, PCB_VEC + andi. %r7, %r18, PCB_VEC beq .L2 bl save_vec @@ -151,17 +150,16 @@ blocked_loop: mr %r3,%r2 /* Get new thread ptr */ bl pmap_activate /* Activate the new address space */ - lwz %r6, PCB_FLAGS(%r17) + lwz %r19, PCB_FLAGS(%r17) /* Restore FPU context if needed */ - andi. %r6, %r6, PCB_FPU + andi. %r6, %r19, PCB_FPU beq .L3 mr %r3,%r2 /* Pass curthread to enable_fpu */ bl enable_fpu .L3: - lwz %r6, PCB_FLAGS(%r17) /* Restore Altivec context if needed */ - andi. %r6, %r6, PCB_VEC + andi. %r6, %r19, PCB_VEC beq .L4 mr %r3,%r2 /* Pass curthread to enable_vec */ bl enable_vec Modified: head/sys/powerpc/powerpc/swtch64.S ============================================================================== --- head/sys/powerpc/powerpc/swtch64.S Fri Apr 26 22:18:22 2019 (r346770) +++ head/sys/powerpc/powerpc/swtch64.S Sat Apr 27 00:53:41 2019 (r346771) @@ -125,26 +125,24 @@ ENTRY(cpu_switch) stdu %r1,-48(%r1) - lwz %r7, PCB_FLAGS(%r17) - andi. %r7, %r7, PCB_CDSCR + lwz %r18, PCB_FLAGS(%r17) + andi. %r7, %r18, PCB_CDSCR beq .L0 /* Custom DSCR was set. Reseting it to enter kernel */ - li %r7, 0x0 - mtspr SPR_DSCR, %r7 + li %r6, 0x0 + mtspr SPR_DSCR, %r6 .L0: - lwz %r7,PCB_FLAGS(%r17) /* Save FPU context if needed */ - andi. %r7, %r7, PCB_FPU + andi. %r7, %r18, PCB_FPU beq .L1 bl save_fpu nop .L1: mr %r3,%r14 /* restore old thread ptr */ - lwz %r7,PCB_FLAGS(%r17) /* Save Altivec context if needed */ - andi. %r7, %r7, PCB_VEC + andi. %r7, %r18, PCB_VEC beq .L2 bl save_vec nop @@ -186,30 +184,28 @@ blocked_loop: bl pmap_activate /* Activate the new address space */ nop - lwz %r6, PCB_FLAGS(%r17) + lwz %r19, PCB_FLAGS(%r17) /* Restore FPU context if needed */ - andi. %r6, %r6, PCB_FPU + andi. %r6, %r19, PCB_FPU beq .L3 mr %r3,%r13 /* Pass curthread to enable_fpu */ bl enable_fpu nop .L3: - lwz %r6, PCB_FLAGS(%r17) /* Restore Altivec context if needed */ - andi. %r6, %r6, PCB_VEC + andi. %r6, %r19, PCB_VEC beq .L31 mr %r3,%r13 /* Pass curthread to enable_vec */ bl enable_vec nop .L31: - lwz %r6, PCB_FLAGS(%r17) /* Restore Custom DSCR if needed */ - andi. %r6, %r6, PCB_CDSCR + andi. %r6, %r19, PCB_CDSCR beq .L4 - ld %r6, PCB_DSCR(%r17) /* Load the DSCR register*/ - mtspr SPR_DSCR, %r6 + ld %r7, PCB_DSCR(%r17) /* Load the DSCR register*/ + mtspr SPR_DSCR, %r7 /* thread to restore is in r3 */ .L4: