Date: Tue, 03 Sep 2019 14:08:21 -0000 From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r346619 - head/sys/powerpc/aim Message-ID: <201904240251.x3O2pwd0008362@repo.freebsd.org>
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Author: jhibbits Date: Wed Apr 24 02:51:58 2019 New Revision: 346619 URL: https://svnweb.freebsd.org/changeset/base/346619 Log: powerpc: Add a couple missing isyncs mtmsr and mtsr require context synchronizing instructions to follow. Without a CSI, there's a chance for a machine check exception. This reportedly does occur on a MPC750 (PowerMac G3). Reported by: Mark Millard Modified: head/sys/powerpc/aim/trap_subr32.S Modified: head/sys/powerpc/aim/trap_subr32.S ============================================================================== --- head/sys/powerpc/aim/trap_subr32.S Wed Apr 24 01:11:50 2019 (r346618) +++ head/sys/powerpc/aim/trap_subr32.S Wed Apr 24 02:51:58 2019 (r346619) @@ -68,7 +68,7 @@ lwzu sr,PM_SR(pmap); \ RESTORE_SRS(pmap,sr) \ /* Restore SR 12 */ \ - lwz sr,12*4(pmap); mtsr 12,sr + lwz sr,12*4(pmap); mtsr 12,sr; isync /* * Kernel SRs are loaded directly from kernel_pmap_ @@ -799,6 +799,7 @@ CNAME(trapexit): mfmsr %r3 andi. %r3,%r3,~PSL_EE@l mtmsr %r3 + isync /* Test AST pending: */ lwz %r5,FRAME_SRR1+8(%r1) mtcr %r5
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