Date: Tue, 15 Nov 2022 17:32:02 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 8a2adde1e4b3 - main - Split out the arm64 EL2 exception vectors Message-ID: <202211151732.2AFHW2EY013109@gitrepo.freebsd.org>
next in thread | raw e-mail | index | archive | help
The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=8a2adde1e4b3fb4230cd39c151c79e73e26b575d commit 8a2adde1e4b3fb4230cd39c151c79e73e26b575d Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2022-10-31 15:08:26 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2022-11-15 17:26:52 +0000 Split out the arm64 EL2 exception vectors These were originally in locore.S as they are only needed so we have a valid value to put into the vbar_el2 register. As these will soon be used by bhyve so move them to a new file as we already have with the EL1 exception vectors in exception.S. Obtained from: https://github.com/FreeBSD-UPB/freebsd-src (earlier version) Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation --- sys/arm64/arm64/hyp_stub.S | 65 ++++++++++++++++++++++++++++++++++++++++++++++ sys/arm64/arm64/locore.S | 30 ++------------------- sys/conf/files.arm64 | 1 + 3 files changed, 68 insertions(+), 28 deletions(-) diff --git a/sys/arm64/arm64/hyp_stub.S b/sys/arm64/arm64/hyp_stub.S new file mode 100644 index 000000000000..42f76da95062 --- /dev/null +++ b/sys/arm64/arm64/hyp_stub.S @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017 Alexandru Elisei <alexandru.elisei@gmail.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <machine/asm.h> + +.macro vempty + .align 7 + 1: b 1b +.endm + +/* + * Install a new exception vector table with the base address supplied by the + * parameter in register x0. + */ +.macro vector_stub_el1h_sync + .align 7 + msr vbar_el2, x0 + ERET +.endm + + .align 11 + .globl hyp_stub_vectors +hyp_stub_vectors: + vempty /* Synchronous EL2t */ + vempty /* IRQ EL2t */ + vempty /* FIQ EL2t */ + vempty /* SError EL2t */ + + vempty /* Synchronous EL2h */ + vempty /* IRQ EL2h */ + vempty /* FIQ EL2h */ + vempty /* SError EL2h */ + + vector_stub_el1h_sync /* Synchronous 64-bit EL1 */ + vempty /* IRQ 64-bit EL1 */ + vempty /* FIQ 64-bit EL1 */ + vempty /* SError 64-bit EL1 */ + + vempty /* Synchronous 32-bit EL1 */ + vempty /* IRQ 32-bit EL1 */ + vempty /* FIQ 32-bit EL1 */ + vempty /* SError 32-bit EL1 */ diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index 3b4f2ccc5353..b37442f15f05 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -291,8 +291,8 @@ LENTRY(drop_to_el1) msr cntvoff_el2, xzr /* Hypervisor trap functions */ - adrp x2, hyp_vectors - add x2, x2, :lo12:hyp_vectors + adrp x2, hyp_stub_vectors + add x2, x2, :lo12:hyp_stub_vectors msr vbar_el2, x2 /* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */ @@ -326,32 +326,6 @@ LENTRY(drop_to_el1) .quad SCTLR_RES1 LEND(drop_to_el1) -#define VECT_EMPTY \ - .align 7; \ - 1: b 1b - - .align 11 -hyp_vectors: - VECT_EMPTY /* Synchronous EL2t */ - VECT_EMPTY /* IRQ EL2t */ - VECT_EMPTY /* FIQ EL2t */ - VECT_EMPTY /* Error EL2t */ - - VECT_EMPTY /* Synchronous EL2h */ - VECT_EMPTY /* IRQ EL2h */ - VECT_EMPTY /* FIQ EL2h */ - VECT_EMPTY /* Error EL2h */ - - VECT_EMPTY /* Synchronous 64-bit EL1 */ - VECT_EMPTY /* IRQ 64-bit EL1 */ - VECT_EMPTY /* FIQ 64-bit EL1 */ - VECT_EMPTY /* Error 64-bit EL1 */ - - VECT_EMPTY /* Synchronous 32-bit EL1 */ - VECT_EMPTY /* IRQ 32-bit EL1 */ - VECT_EMPTY /* FIQ 32-bit EL1 */ - VECT_EMPTY /* Error 32-bit EL1 */ - /* * Get the delta between the physical address we were loaded to and the * virtual address we expect to run from. This is used when building the diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 0d47c2e432a1..a009a19b1359 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -51,6 +51,7 @@ arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt +arm64/arm64/hyp_stub.S standard arm64/arm64/identcpu.c standard arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?202211151732.2AFHW2EY013109>