Date: Mon, 29 Jan 2024 21:39:23 +0000 From: bugzilla-noreply@freebsd.org To: toolchain@FreeBSD.org Subject: [Bug 276690] Compilation of a particular module never ends causing runaway builds for the port graphics/diplib on arm64 architecture Message-ID: <bug-276690-29464-RMz382hseV@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-276690-29464@https.bugs.freebsd.org/bugzilla/> References: <bug-276690-29464@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D276690 --- Comment #13 from Dimitry Andric <dim@FreeBSD.org> --- It's weird, I can find an upstream commit that appears to fix this hang, wh= ich is https://github.com/llvm/llvm-project/commit/56e60bc5bbfb8fdf2b22a897e8801c8= 7771c84e8 ("TargetLowering: fix an infinite DAG combine in SimplifySETCC ") but it appears to have already been applied on llvm 17.0.6. E.g. I thought I could apply that change and make it work, but now I am hav= ing trouble reproducing the original hang. :) --=20 You are receiving this mail because: You are the assignee for the bug.=
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