From owner-svn-src-head@FreeBSD.ORG Fri Aug 8 18:36:54 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id A636944A for ; Fri, 8 Aug 2014 18:36:54 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5EC722918 for ; Fri, 8 Aug 2014 18:36:54 +0000 (UTC) Received: from np (uid 1205) (envelope-from np@FreeBSD.org) id 2089 by svn.freebsd.org (DragonFly Mail Agent v0.9+); Fri, 08 Aug 2014 18:36:54 +0000 From: Navdeep Parhar Date: Fri, 8 Aug 2014 18:36:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r269731 - head/sys/dev/cxgbe/common X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-Id: <53e518c6.2089.4cdf9952@svn.freebsd.org> X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Aug 2014 18:36:54 -0000 Author: np Date: Fri Aug 8 18:36:53 2014 New Revision: 269731 URL: http://svnweb.freebsd.org/changeset/base/269731 Log: cxgbe(4): Do not poke T4-only registers on a T5 (and vice versa). Obtained from: Chelsio Communications MFC after: 1 week Modified: head/sys/dev/cxgbe/common/t4_hw.c Modified: head/sys/dev/cxgbe/common/t4_hw.c ============================================================================== --- head/sys/dev/cxgbe/common/t4_hw.c Fri Aug 8 18:00:23 2014 (r269730) +++ head/sys/dev/cxgbe/common/t4_hw.c Fri Aug 8 18:36:53 2014 (r269731) @@ -2077,15 +2077,18 @@ static void pcie_intr_handler(struct ada int fat; - fat = t4_handle_intr_status(adapter, - A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, - sysbus_intr_info) + - t4_handle_intr_status(adapter, - A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, - pcie_port_intr_info) + - t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, - is_t4(adapter) ? - pcie_intr_info : t5_pcie_intr_info); + if (is_t4(adapter)) + fat = t4_handle_intr_status(adapter, + A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, + sysbus_intr_info) + + t4_handle_intr_status(adapter, + A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, + pcie_port_intr_info) + + t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, + pcie_intr_info); + else + fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, + t5_pcie_intr_info); if (fat) t4_fatal_err(adapter); } @@ -2466,9 +2469,15 @@ static void ma_intr_handler(struct adapt { u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); - if (status & F_MEM_PERR_INT_CAUSE) + if (status & F_MEM_PERR_INT_CAUSE) { CH_ALERT(adapter, "MA parity error, parity status %#x\n", - t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS)); + t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); + if (is_t5(adapter)) + CH_ALERT(adapter, + "MA parity error, parity status %#x\n", + t4_read_reg(adapter, + A_MA_PARITY_ERROR_STATUS2)); + } if (status & F_MEM_WRAP_INT_CAUSE) { v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); CH_ALERT(adapter, "MA address wrap-around error by client %u to" @@ -2685,10 +2694,8 @@ void t4_intr_clear(struct adapter *adapt { static const unsigned int cause_reg[] = { A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, - A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, - A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, - A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS, A_MA_INT_CAUSE, + A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), @@ -2710,6 +2717,14 @@ void t4_intr_clear(struct adapter *adapt t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : A_MC_P_INT_CAUSE, 0xffffffff); + if (is_t4(adapter)) { + t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, + 0xffffffff); + t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, + 0xffffffff); + } else + t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); + t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ }