From owner-svn-src-head@freebsd.org Wed Aug 15 14:19:09 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 45AFB105534E; Wed, 15 Aug 2018 14:19:09 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id EFF4F8F0C1; Wed, 15 Aug 2018 14:19:08 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id B71AD38AD; Wed, 15 Aug 2018 14:19:08 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w7FEJ8oL058976; Wed, 15 Aug 2018 14:19:08 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w7FEJ8rK058973; Wed, 15 Aug 2018 14:19:08 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201808151419.w7FEJ8rK058973@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Wed, 15 Aug 2018 14:19:08 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r337847 - in head/sys/arm: arm include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys/arm: arm include X-SVN-Commit-Revision: 337847 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Aug 2018 14:19:09 -0000 Author: andrew Date: Wed Aug 15 14:19:07 2018 New Revision: 337847 URL: https://svnweb.freebsd.org/changeset/base/337847 Log: Remove ARM_MMU_GENERIC, it's the only ARMV4/v5 MMU we support. Sponsored by: DARPA, AFRL Modified: head/sys/arm/arm/pmap-v4.c head/sys/arm/include/pmap-v4.h Modified: head/sys/arm/arm/pmap-v4.c ============================================================================== --- head/sys/arm/arm/pmap-v4.c Wed Aug 15 13:52:31 2018 (r337846) +++ head/sys/arm/arm/pmap-v4.c Wed Aug 15 14:19:07 2018 (r337847) @@ -447,7 +447,6 @@ kernel_pt_lookup(vm_paddr_t pa) return (0); } -#if ARM_MMU_GENERIC != 0 void pmap_pte_init_generic(void) { @@ -485,8 +484,6 @@ pmap_pte_init_generic(void) pte_l2_s_proto = L2_S_PROTO_generic; } -#endif /* ARM_MMU_GENERIC != 0 */ - /* * Allocate an L1 translation table for the specified pmap. * This is called at pmap creation time. @@ -3771,7 +3768,6 @@ pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t ev * StrongARM accesses to non-cached pages are non-burst making writing * _any_ bulk data very slow. */ -#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3) void pmap_zero_page_generic(vm_paddr_t phys, int off, int size) { @@ -3798,7 +3794,6 @@ pmap_zero_page_generic(vm_paddr_t phys, int off, int s mtx_unlock(&cmtx); } -#endif /* ARM_MMU_GENERIC != 0 */ /* * pmap_zero_page zeros the specified hardware page by mapping @@ -3930,7 +3925,6 @@ pmap_clean_page(struct pv_entry *pv, boolean_t is_src) * hook points. The same comment regarding cachability as in * pmap_zero_page also applies here. */ -#if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3) void pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) { @@ -3995,7 +3989,6 @@ pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offs cpu_l2cache_inv_range(csrcp + a_offs, cnt); cpu_l2cache_wbinv_range(cdstp + b_offs, cnt); } -#endif /* ARM_MMU_GENERIC != 0 */ void pmap_copy_page(vm_page_t src, vm_page_t dst) Modified: head/sys/arm/include/pmap-v4.h ============================================================================== --- head/sys/arm/include/pmap-v4.h Wed Aug 15 13:52:31 2018 (r337846) +++ head/sys/arm/include/pmap-v4.h Wed Aug 15 14:19:07 2018 (r337847) @@ -53,22 +53,6 @@ #include /* - * Define the MMU types we support based on the cpu types. While the code has - * some theoretical support for multiple MMU types in a single kernel, there are - * no actual working configurations that use that feature. - */ -#if defined(CPU_ARM9E) -#define ARM_MMU_GENERIC 1 -#else -#define ARM_MMU_GENERIC 0 -#endif - -#define ARM_NMMUS (ARM_MMU_GENERIC) -#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) -#error ARM_NMMUS is 0 -#endif - -/* * Pte related macros */ #define PTE_NOCACHE 1 @@ -306,21 +290,6 @@ extern int pmap_needs_pte_sync; */ #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) -#if ARM_NMMUS > 1 -/* More than one MMU class configured; use variables. */ -#define L2_S_PROT_U pte_l2_s_prot_u -#define L2_S_PROT_W pte_l2_s_prot_w -#define L2_S_PROT_MASK pte_l2_s_prot_mask - -#define L1_S_CACHE_MASK pte_l1_s_cache_mask -#define L2_L_CACHE_MASK pte_l2_l_cache_mask -#define L2_S_CACHE_MASK pte_l2_s_cache_mask - -#define L1_S_PROTO pte_l1_s_proto -#define L1_C_PROTO pte_l1_c_proto -#define L2_S_PROTO pte_l2_s_proto - -#elif ARM_MMU_GENERIC != 0 #define L2_S_PROT_U L2_S_PROT_U_generic #define L2_S_PROT_W L2_S_PROT_W_generic #define L2_S_PROT_MASK L2_S_PROT_MASK_generic @@ -333,8 +302,6 @@ extern int pmap_needs_pte_sync; #define L1_C_PROTO L1_C_PROTO_generic #define L2_S_PROTO L2_S_PROTO_generic -#endif /* ARM_NMMUS > 1 */ - #if defined(CPU_XSCALE_81342) #define CPU_XSCALE_CORE3 #define PMAP_NEEDS_PTE_SYNC 1 @@ -438,12 +405,10 @@ extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_p vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); -#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_81342) void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); void pmap_zero_page_generic(vm_paddr_t, int, int); void pmap_pte_init_generic(void); -#endif /* ARM_MMU_GENERIC != 0 */ #if defined(CPU_XSCALE_81342) #define ARM_HAVE_SUPERSECTIONS