Skip site navigation (1)Skip section navigation (2)
Date:      Thu, 23 May 2019 17:35:40 +0000 (UTC)
From:      Emmanuel Vadot <manu@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r348180 - in head/sys: arm/allwinner arm/allwinner/clkng conf
Message-ID:  <201905231735.x4NHZedG037286@repo.freebsd.org>

next in thread | raw e-mail | index | archive | help
Author: manu
Date: Thu May 23 17:35:40 2019
New Revision: 348180
URL: https://svnweb.freebsd.org/changeset/base/348180

Log:
  arm: allwinner: clk: Add new clock aw_clk_frac
  
  Add a clock driver for clock that can either be used in integer mode
  with one N factor and one M divider or in fractional mode where the
  output frequency is chosen between two predifined output.

Added:
  head/sys/arm/allwinner/clkng/aw_clk_frac.c   (contents, props changed)
  head/sys/arm/allwinner/clkng/aw_clk_frac.h   (contents, props changed)
Modified:
  head/sys/arm/allwinner/clkng/aw_ccung.c
  head/sys/arm/allwinner/clkng/aw_ccung.h
  head/sys/arm/allwinner/clkng/aw_clk.h
  head/sys/arm/allwinner/files.allwinner
  head/sys/conf/files.arm64

Modified: head/sys/arm/allwinner/clkng/aw_ccung.c
==============================================================================
--- head/sys/arm/allwinner/clkng/aw_ccung.c	Thu May 23 17:34:33 2019	(r348179)
+++ head/sys/arm/allwinner/clkng/aw_ccung.c	Thu May 23 17:35:40 2019	(r348180)
@@ -305,6 +305,9 @@ aw_ccung_attach(device_t dev)
 			aw_clk_prediv_mux_register(sc->clkdom,
 			    sc->clks[i].clk.prediv_mux);
 			break;
+		case AW_CLK_FRAC:
+			aw_clk_frac_register(sc->clkdom, sc->clks[i].clk.frac);
+			break;
 		}
 	}
 

Modified: head/sys/arm/allwinner/clkng/aw_ccung.h
==============================================================================
--- head/sys/arm/allwinner/clkng/aw_ccung.h	Thu May 23 17:34:33 2019	(r348179)
+++ head/sys/arm/allwinner/clkng/aw_ccung.h	Thu May 23 17:35:40 2019	(r348180)
@@ -34,6 +34,7 @@
 #include <arm/allwinner/clkng/aw_clk_nkmp.h>
 #include <arm/allwinner/clkng/aw_clk_nm.h>
 #include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
+#include <arm/allwinner/clkng/aw_clk_frac.h>
 #include <dev/extres/clk/clk_mux.h>
 #include <dev/extres/clk/clk_div.h>
 #include <dev/extres/clk/clk_fixed.h>
@@ -46,6 +47,7 @@ enum aw_ccung_clk_type {
 	AW_CLK_NKMP,
 	AW_CLK_NM,
 	AW_CLK_PREDIV_MUX,
+	AW_CLK_FRAC,
 };
 
 struct aw_ccung_clk {
@@ -57,6 +59,7 @@ struct aw_ccung_clk {
 		struct aw_clk_nkmp_def		*nkmp;
 		struct aw_clk_nm_def		*nm;
 		struct aw_clk_prediv_mux_def	*prediv_mux;
+		struct aw_clk_frac_def		*frac;
 	} clk;
 };
 

Modified: head/sys/arm/allwinner/clkng/aw_clk.h
==============================================================================
--- head/sys/arm/allwinner/clkng/aw_clk.h	Thu May 23 17:34:33 2019	(r348179)
+++ head/sys/arm/allwinner/clkng/aw_clk.h	Thu May 23 17:35:40 2019	(r348180)
@@ -309,6 +309,38 @@ aw_clk_factor_get_value(struct aw_clk_factor *factor, 
 		.flags = _flags | AW_CLK_HAS_UPDATE,	\
 	}
 
+#define FRAC_CLK(_clkname, _id, _name, _pnames,	\
+     _offset,						\
+     _nshift, _nwidth, _nvalue, _nflags,		\
+     _mshift, _mwidth, _mvalue, _mflags,		\
+     _gate_shift, _lock_shift,_lock_retries,		\
+    _flags, _freq0, _freq1, _mode_sel, _freq_sel)	\
+	static struct aw_clk_frac_def _clkname = {	\
+		.clkdef = {				\
+			.id = _id,			\
+			.name = _name,			\
+			.parent_names = _pnames,	\
+			.parent_cnt = nitems(_pnames),	\
+		},					\
+		.offset = _offset,			\
+		.n.shift = _nshift,			\
+		.n.width = _nwidth,			\
+		.n.value = _nvalue,			\
+		.n.flags = _nflags,			\
+		.m.shift = _mshift,			\
+		.m.width = _mwidth,			\
+		.m.value = _mvalue,			\
+		.m.flags = _mflags,			\
+		.gate_shift = _gate_shift,		\
+		.lock_shift = _lock_shift,		\
+		.lock_retries = _lock_retries,		\
+		.flags = _flags | AW_CLK_HAS_FRAC,	\
+		.frac.freq0 = _freq0,			\
+		.frac.freq1 = _freq1,			\
+		.frac.mode_sel = _mode_sel,		\
+		.frac.freq_sel = _freq_sel,		\
+	}
+
 #define NM_CLK(_clkname, _id, _name, _pnames,		\
      _offset,						\
      _nshift, _nwidth, _nvalue, _nflags,		\

Added: head/sys/arm/allwinner/clkng/aw_clk_frac.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/arm/allwinner/clkng/aw_clk_frac.c	Thu May 23 17:35:40 2019	(r348180)
@@ -0,0 +1,338 @@
+/*-
+ * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <dev/extres/clk/clk.h>
+
+#include <arm/allwinner/clkng/aw_clk.h>
+#include <arm/allwinner/clkng/aw_clk_frac.h>
+
+#include "clkdev_if.h"
+
+/*
+ * clknode for clocks matching the formula :
+ *
+ * clk = (24Mhz * n) / m in integer mode
+ * clk = frac_out1 or frac_out2 in fractional mode
+ *
+ */
+
+struct aw_clk_frac_sc {
+	uint32_t	offset;
+
+	struct aw_clk_factor	m;
+	struct aw_clk_factor	n;
+	struct aw_clk_frac	frac;
+
+	uint32_t	mux_shift;
+	uint32_t	mux_mask;
+	uint32_t	gate_shift;
+	uint32_t	lock_shift;
+	uint32_t	lock_retries;
+
+	uint32_t	flags;
+};
+
+#define	WRITE4(_clk, off, val)						\
+	CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
+#define	READ4(_clk, off, val)						\
+	CLKDEV_READ_4(clknode_get_device(_clk), off, val)
+#define	DEVICE_LOCK(_clk)							\
+	CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
+#define	DEVICE_UNLOCK(_clk)						\
+	CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
+
+static int
+aw_clk_frac_init(struct clknode *clk, device_t dev)
+{
+	struct aw_clk_frac_sc *sc;
+	uint32_t val, idx;
+
+	sc = clknode_get_softc(clk);
+
+	idx = 0;
+	if ((sc->flags & AW_CLK_HAS_MUX) != 0) {
+		DEVICE_LOCK(clk);
+		READ4(clk, sc->offset, &val);
+		DEVICE_UNLOCK(clk);
+
+		idx = (val & sc->mux_mask) >> sc->mux_shift;
+	}
+
+	clknode_init_parent_idx(clk, idx);
+	return (0);
+}
+
+static int
+aw_clk_frac_set_gate(struct clknode *clk, bool enable)
+{
+	struct aw_clk_frac_sc *sc;
+	uint32_t val;
+
+	sc = clknode_get_softc(clk);
+
+	if ((sc->flags & AW_CLK_HAS_GATE) == 0)
+		return (0);
+
+	DEVICE_LOCK(clk);
+	READ4(clk, sc->offset, &val);
+	if (enable)
+		val |= (1 << sc->gate_shift);
+	else
+		val &= ~(1 << sc->gate_shift);
+	WRITE4(clk, sc->offset, val);
+	DEVICE_UNLOCK(clk);
+
+	return (0);
+}
+
+static int
+aw_clk_frac_set_mux(struct clknode *clk, int index)
+{
+	struct aw_clk_frac_sc *sc;
+	uint32_t val;
+
+	sc = clknode_get_softc(clk);
+
+	if ((sc->flags & AW_CLK_HAS_MUX) == 0)
+		return (0);
+
+	DEVICE_LOCK(clk);
+	READ4(clk, sc->offset, &val);
+	val &= ~sc->mux_mask;
+	val |= index << sc->mux_shift;
+	WRITE4(clk, sc->offset, val);
+	DEVICE_UNLOCK(clk);
+
+	return (0);
+}
+
+static uint64_t
+aw_clk_frac_find_best(struct aw_clk_frac_sc *sc, uint64_t fparent, uint64_t *fout,
+    uint32_t *factor_n, uint32_t *factor_m)
+{
+	uint64_t cur, best;
+	uint32_t m, n, max_m, max_n, min_m, min_n;
+
+	*factor_n = *factor_m = 0;
+	best = cur = 0;
+
+	max_m = aw_clk_factor_get_max(&sc->m);
+	max_n = aw_clk_factor_get_max(&sc->n);
+	min_m = aw_clk_factor_get_min(&sc->m);
+	min_n = aw_clk_factor_get_min(&sc->n);
+
+	for (n = min_n; n <= max_n; n++) {
+		for (m = min_m; m <= max_m; m++) {
+			cur = fparent * n / m;
+			if ((*fout - cur) < (*fout - best)) {
+				best = cur;
+				*factor_n = n;
+				*factor_m = m;
+			}
+			if (best == *fout)
+				return (best);
+		}
+	}
+
+	return (best);
+}
+
+static int
+aw_clk_frac_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
+    int flags, int *stop)
+{
+	struct aw_clk_frac_sc *sc;
+	uint64_t cur, best, best_frac;
+	uint32_t val, m, n, best_m, best_n;
+	int retry;
+
+	sc = clknode_get_softc(clk);
+
+	best = best_frac = cur = 0;
+
+	if (*fout == sc->frac.freq0)
+		best = best_frac = sc->frac.freq0;
+	else if (*fout == sc->frac.freq1)
+		best = best_frac = sc->frac.freq1;
+	else
+		best = aw_clk_frac_find_best(sc, fparent, fout,
+		    &best_n, &best_m);
+
+	if ((flags & CLK_SET_DRYRUN) != 0) {
+		*fout = best;
+		*stop = 1;
+		return (0);
+	}
+
+	if ((best < *fout) &&
+	  ((flags & CLK_SET_ROUND_DOWN) == 0)) {
+		*stop = 1;
+		return (ERANGE);
+	}
+	if ((best > *fout) &&
+	  ((flags & CLK_SET_ROUND_UP) == 0)) {
+		*stop = 1;
+		return (ERANGE);
+	}
+
+	DEVICE_LOCK(clk);
+	READ4(clk, sc->offset, &val);
+	/* Disable clock during freq changes */
+	val &= ~(1 << sc->gate_shift);
+	WRITE4(clk, sc->offset, val);
+
+	if (best_frac != 0) {
+		val &= ~sc->frac.mode_sel;
+		/* M should be 0 per the manual */
+		val &= ~sc->m.mask;
+		if (best_frac == sc->frac.freq0)
+			val &= ~sc->frac.freq_sel;
+		else
+			val |= sc->frac.freq_sel;
+	} else {
+		val |= sc->frac.mode_sel; /* Select integer mode */
+		n = aw_clk_factor_get_value(&sc->n, best_n);
+		m = aw_clk_factor_get_value(&sc->m, best_m);
+		val &= ~sc->n.mask;
+		val &= ~sc->m.mask;
+		val |= n << sc->n.shift;
+		val |= m << sc->m.shift;
+	}
+
+	/* Write the clock changes */
+	WRITE4(clk, sc->offset, val);
+
+	/* Enable clock now that we've change it */
+	val |= 1 << sc->gate_shift;
+	WRITE4(clk, sc->offset, val);
+	DEVICE_UNLOCK(clk);
+
+	for (retry = 0; retry < sc->lock_retries; retry++) {
+		READ4(clk, sc->offset, &val);
+		if ((val & (1 << sc->lock_shift)) != 0)
+			break;
+		DELAY(1000);
+	}
+
+	*fout = best;
+	*stop = 1;
+
+	return (0);
+}
+
+static int
+aw_clk_frac_recalc(struct clknode *clk, uint64_t *freq)
+{
+	struct aw_clk_frac_sc *sc;
+	uint32_t val, m, n;
+
+	sc = clknode_get_softc(clk);
+
+	DEVICE_LOCK(clk);
+	READ4(clk, sc->offset, &val);
+	DEVICE_UNLOCK(clk);
+
+	if ((val & sc->frac.mode_sel) == 0) {
+		if (val & sc->frac.freq_sel)
+			*freq = sc->frac.freq1;
+		else
+			*freq = sc->frac.freq0;
+	} else {
+		m = aw_clk_get_factor(val, &sc->m);
+		n = aw_clk_get_factor(val, &sc->n);
+
+		*freq = *freq * n / m;
+	}
+
+	return (0);
+}
+
+static clknode_method_t aw_frac_clknode_methods[] = {
+	/* Device interface */
+	CLKNODEMETHOD(clknode_init,		aw_clk_frac_init),
+	CLKNODEMETHOD(clknode_set_gate,		aw_clk_frac_set_gate),
+	CLKNODEMETHOD(clknode_set_mux,		aw_clk_frac_set_mux),
+	CLKNODEMETHOD(clknode_recalc_freq,	aw_clk_frac_recalc),
+	CLKNODEMETHOD(clknode_set_freq,		aw_clk_frac_set_freq),
+	CLKNODEMETHOD_END
+};
+
+DEFINE_CLASS_1(aw_frac_clknode, aw_frac_clknode_class, aw_frac_clknode_methods,
+    sizeof(struct aw_clk_frac_sc), clknode_class);
+
+int
+aw_clk_frac_register(struct clkdom *clkdom, struct aw_clk_frac_def *clkdef)
+{
+	struct clknode *clk;
+	struct aw_clk_frac_sc *sc;
+
+	clk = clknode_create(clkdom, &aw_frac_clknode_class, &clkdef->clkdef);
+	if (clk == NULL)
+		return (1);
+
+	sc = clknode_get_softc(clk);
+
+	sc->offset = clkdef->offset;
+
+	sc->m.shift = clkdef->m.shift;
+	sc->m.width = clkdef->m.width;
+	sc->m.mask = ((1 << sc->m.width) - 1) << sc->m.shift;
+	sc->m.value = clkdef->m.value;
+	sc->m.flags = clkdef->m.flags;
+
+	sc->n.shift = clkdef->n.shift;
+	sc->n.width = clkdef->n.width;
+	sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
+	sc->n.value = clkdef->n.value;
+	sc->n.flags = clkdef->n.flags;
+
+	sc->frac.freq0 = clkdef->frac.freq0;
+	sc->frac.freq1 = clkdef->frac.freq1;
+	sc->frac.mode_sel = 1 << clkdef->frac.mode_sel;
+	sc->frac.freq_sel = 1 << clkdef->frac.freq_sel;
+
+	sc->mux_shift = clkdef->mux_shift;
+	sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift;
+
+	sc->gate_shift = clkdef->gate_shift;
+
+	sc->lock_shift = clkdef->lock_shift;
+	sc->lock_retries = clkdef->lock_retries;
+
+	sc->flags = clkdef->flags;
+
+	clknode_register(clkdom, clk);
+
+	return (0);
+}

Added: head/sys/arm/allwinner/clkng/aw_clk_frac.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/arm/allwinner/clkng/aw_clk_frac.h	Thu May 23 17:35:40 2019	(r348180)
@@ -0,0 +1,52 @@
+/*-
+ * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	__AW_CLK_FRAC_H__
+#define __AW_CLK_FRAC_H__
+
+#include <dev/extres/clk/clk.h>
+
+struct aw_clk_frac_def {
+	struct clknode_init_def clkdef;
+	uint32_t		offset;
+
+	struct aw_clk_factor	m;
+	struct aw_clk_factor	n;
+	struct aw_clk_frac	frac;
+
+	uint32_t		mux_shift;
+	uint32_t		mux_width;
+	uint32_t		gate_shift;
+	uint32_t		lock_shift;
+	uint32_t		lock_retries;
+
+	uint32_t		flags;
+};
+
+int	aw_clk_frac_register(struct clkdom *clkdom, struct aw_clk_frac_def *clkdef);
+
+#endif /* __AW_CLK_FRAC_H__ */

Modified: head/sys/arm/allwinner/files.allwinner
==============================================================================
--- head/sys/arm/allwinner/files.allwinner	Thu May 23 17:34:33 2019	(r348179)
+++ head/sys/arm/allwinner/files.allwinner	Thu May 23 17:35:40 2019	(r348180)
@@ -36,6 +36,7 @@ arm/allwinner/aw_ccu.c			standard
 arm/allwinner/aw_gmacclk.c		standard
 
 arm/allwinner/clkng/aw_ccung.c		standard
+arm/allwinner/clkng/aw_clk_frac.c	standard
 arm/allwinner/clkng/aw_clk_nkmp.c	standard
 arm/allwinner/clkng/aw_clk_nm.c		standard
 arm/allwinner/clkng/aw_clk_prediv_mux.c	standard

Modified: head/sys/conf/files.arm64
==============================================================================
--- head/sys/conf/files.arm64	Thu May 23 17:34:33 2019	(r348179)
+++ head/sys/conf/files.arm64	Thu May 23 17:35:40 2019	(r348180)
@@ -49,6 +49,7 @@ arm/allwinner/if_awg.c		optional	awg ext_resources sys
 
 # Allwinner clock driver
 arm/allwinner/clkng/aw_ccung.c		optional	aw_ccu fdt
+arm/allwinner/clkng/aw_clk_frac.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nkmp.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nm.c		optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_prediv_mux.c	optional	aw_ccu fdt



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201905231735.x4NHZedG037286>