Date: Thu, 21 Nov 1996 05:35:30 +0800 From: Peter Wemm <peter@spinner.dialix.com> To: Steve Passe <smp@csn.net> Cc: cbrown@aracnet.com, Barney Wolff <barney@databus.com>, freebsd-smp@freebsd.org Subject: Re: reinventing vs copying Message-ID: <199611202135.FAA13316@spinner.DIALix.COM> In-Reply-To: Your message of "Tue, 19 Nov 1996 21:59:04 MST." <199611200459.VAA22372@clem.systemsix.com>
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Steve Passe wrote: > The 8259 ICU latches an INT that occurs while that INT is masked. > The IO APIC looses any INT occuring while that INT is masked. > Intel calls this a "design consideration", I call it "brain damage". Also, don't forget, there are two types of masking with the apic system. (beware, I don't have the docs in front of me, I'm going from stale memory. Please be gentle :-) First: There is the single on/off bit in the IO apic registers. This is slow to get at and quite cumbersome, since it involves bit shuffling and accessing hardware via a bank-switched register system. This method looses edge triggered interrupts if they occur while the APIC pin is turned off (no real suprise there). Second: There is the local mask on the CPU, combined with focus processing. This method has advantages and disadvantages. It has a "pending" register so that it doesn't loose edge triggered interrupts. "Focus processing" means that while CPU 'n' is servicing a particular interrupt, the IO apic's route *all* further interrupts of that type to that processor. This is necessary since the local mask is per-cpu and this is how it prevents the handlers from interrupting themselves. It implements a priority system. The source IRQ is implicitly masked and unmasked during execution of the handler with no extra work by the OS, other than hitting the EOI register at the end. The big problem with approach #2 is that it's completely different to the way FreeBSD's traditional 8259-based interrupt system was implemented. It requires that you prioritise interrupts in numerical order (or you have to deal with 256-bit masking), and you have to choose things like whether splimp() is greater or less than spltty(). Also, you're dealing with 256 bit registers on a per-cpu basis, ie: cpu 2 cannot see what's masked in cpu 1's registers (without an APIC remote read) and so on. Since the IRQ system needs to be redone to handle > 32 interrupts since: - we need to be able to have the 8259's online for some (current) hardware. - we need to be able to deal with more than 1 IO apic. - we need to be able to deal with IPI's, and be able to mask them etc. I personally think that the right "temporary" solution for the edge trigger problem is to never disable the IO apic pin (for edge only), and simply wear the cost of the relatively rare occasions when the interrupts *do* interrupt their own handlers. Cheers, -Peter
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