Date: Wed, 20 Jan 2021 18:33:18 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 8e67b9389df1 - main - Handle arm64 undefied instructions on msr exceptions Message-ID: <202101201833.10KIXIt9019320@gitrepo.freebsd.org>
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The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=8e67b9389df12d36ef4bc6bf2a7f2e60e3bcd94a commit 8e67b9389df12d36ef4bc6bf2a7f2e60e3bcd94a Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2021-01-20 09:56:47 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2021-01-20 17:59:38 +0000 Handle arm64 undefied instructions on msr exceptions When userspace tries to access a special register that it doesn't have access to the kernel receives an exception. On most cores this exception has been observed to be the undefined instruction exception, however on the Apple M1 under a QEMU based hypervisor it can be the MSR exception. Handle this second case by also running the undefined exception handler on these exceptions. Sponsored by: Innovate UK --- sys/arm64/arm64/trap.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/sys/arm64/arm64/trap.c b/sys/arm64/arm64/trap.c index 12d10ff1d261..0b2d4760cea3 100644 --- a/sys/arm64/arm64/trap.c +++ b/sys/arm64/arm64/trap.c @@ -535,8 +535,14 @@ do_el0_sync(struct thread *td, struct trapframe *frame) userret(td, frame); break; case EXCP_MSR: - call_trapsignal(td, SIGILL, ILL_PRVOPC, (void *)frame->tf_elr, - exception); + /* + * The CPU can raise EXCP_MSR when userspace executes an mrs + * instruction to access a special register userspace doesn't + * have access to. + */ + if (!undef_insn(0, frame)) + call_trapsignal(td, SIGILL, ILL_PRVOPC, + (void *)frame->tf_elr, exception); userret(td, frame); break; case EXCP_SOFTSTP_EL0:
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