Date: Mon, 9 Feb 2015 11:59:51 +0000 From: "zbb (Zbigniew Bodek)" <phabric-noreply@FreeBSD.org> To: freebsd-arm@freebsd.org Subject: [Differential] [Request, 54 lines] D1812: Resolve cache line size from CP15 Message-ID: <differential-rev-PHID-DREV-conagpb5joeuzmkcxv34-req@FreeBSD.org>
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zbb created this revision. zbb added reviewers: ian, andrew. zbb added a subscriber: freebsd-arm. REVISION SUMMARY Switch the cache line size during invalidations/flushes to be read from CP15 cache type register. Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf REVISION DETAIL https://reviews.freebsd.org/D1812 AFFECTED FILES sys/arm/arm/cpufunc.c sys/arm/arm/cpufunc_asm_armv7.S sys/arm/arm/elf_trampoline.c sys/arm/include/armreg.h To: zbb, ian, andrew Cc: freebsd-arm
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