From owner-p4-projects@FreeBSD.ORG Mon Oct 22 21:23:13 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id D9E9F593; Mon, 22 Oct 2012 21:23:12 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 80F52591 for ; Mon, 22 Oct 2012 21:23:12 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 5F03D8FC08 for ; Mon, 22 Oct 2012 21:23:12 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q9MLNCgX038997 for ; Mon, 22 Oct 2012 21:23:12 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q9MLNCLd038994 for perforce@freebsd.org; Mon, 22 Oct 2012 21:23:12 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Mon, 22 Oct 2012 21:23:12 GMT Message-Id: <201210222123.q9MLNCLd038994@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson Subject: PERFORCE change 218927 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.14 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Oct 2012 21:23:13 -0000 http://p4web.freebsd.org/@@218927?ac=10 Change 218927 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/10/22 21:22:46 Now that immediate-indexed notation is supported for CHERI CLC and CSC, use it. It's not quite the syntax documented in the manual, but it still allows us to lose assertions that immediate offsets are 0, which will improve context switch code significantly. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#8 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#8 (text+ko) ==== @@ -153,24 +153,12 @@ /* * Capability store; while this doesn't muck with c0, it does require a memory * clobber. - * - * XXXRW: The assembler does not yet support base+offset, just base, so assert - * that offset (for now) is not permitted. */ -#ifdef _KERNEL #define CHERI_CSC(cs, cb, regbase, offset) do { \ - KASSERT((offset) == 0, \ - ("CHERI_CSC: non-zero offset not supported")); \ - __asm__ __volatile__ ("csc $c%0, %1($c%2)" : : \ - "i" (cs), "r" (regbase), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csc $c%0, %1, %2($c%3)" : : \ + "i" (cs), "r" (regbase), "i" (offset), "i" (cb) : \ + "memory"); \ } while (0) -#else -#define CHERI_CSC(cs, cb, regbase, offset) do { \ - assert((offset) == 0); \ - __asm__ __volatile__ ("csc $c%0, %1($c%2)" : : \ - "i" (cs), "r" (regbase), "i" (cb) : "memory"); \ -} while (0) -#endif /* * Routines that modify or replace values in capability registers, and that if @@ -233,32 +221,15 @@ "i" (cd), "i" (cb), "r" (v)); \ } while (0) -/* - * XXXRW: The assembler does not yet support base+offset, just base, so assert - * that offset (for now) is not permitted. - */ -#ifdef _KERNEL #define CHERI_CLC(cd, cb, regbase, offset) do { \ - KASSERT((offset) == 0, \ - ("CHERI_CLC: non-zero offset not supported")); \ if ((cd) == 0) \ - __asm__ __volatile__ ("clc $c%0, %1($c%2)" : : \ - "i" (cd), "r" (regbase), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clc $c%0, %1, %2($c%3)" : : \ + "i" (cd), "r" (regbase), "i" (offset), "i" (cb) : \ + "memory"); \ else \ - __asm__ __volatile__ ("clc $c%0, %1($c%2)" : : \ - "i" (cd), "r" (regbase), "i" (cb)); \ + __asm__ __volatile__ ("clc $c%0, %1, %2($c%3)" : : \ + "i" (cd), "r" (regbase), "i" (offset), "i" (cb)); \ } while (0) -#else -#define CHERI_CLC(cd, cb, regbase, offset) do { \ - assert((offset) == 0); \ - if ((cd) == 0) \ - __asm__ __volatile__ ("clc $c%0, %1($c%2)" : : \ - "i" (cd), "r" (regbase), "i" (cb) : "memory"); \ - else \ - __asm__ __volatile__ ("clc $c%0, %1($c%2)" : : \ - "i" (cd), "r" (regbase), "i" (cb)); \ -} while (0) -#endif static inline void cp2_capability_load(u_int crn_to, struct chericap *cp)