From owner-freebsd-arm@freebsd.org Fri Aug 28 07:15:51 2015 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BD1BC9C4208 for ; Fri, 28 Aug 2015 07:15:51 +0000 (UTC) (envelope-from mihai.carabas@gmail.com) Received: from mail-wi0-x22f.google.com (mail-wi0-x22f.google.com [IPv6:2a00:1450:400c:c05::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 5B348EF1 for ; Fri, 28 Aug 2015 07:15:51 +0000 (UTC) (envelope-from mihai.carabas@gmail.com) Received: by wibcx1 with SMTP id cx1so4268658wib.1 for ; Fri, 28 Aug 2015 00:15:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=FP+JJi029TPHcQ44FH9BPnlCmi7Lt5BHE3nsDKBy6eU=; b=CnzC5uKjxhG8Zv1DhlJb9h4NRhcYr5B9kHg5PjObtOquPtA8ELro9RcJxcqbnneenG Fr7d+tXNx1GqMIHv4QEI1zDOzVprvfCM62L6MTTMQyFxA6aJmlqFSRI+CF/nVxAQ4qEZ 6Wxg24oXUdRP/+PA2L0hjQIdpEVkqB/7ovvmbPw417PhXeh6HWQArA4xlL5R8t8EBDPA CzEC3ZPuMt6MxBXRWcymDbPO8+U/+8duYUQRCo87xAO8ECRMY05a+H070bFRCBDZqzva PGCG0bMR/LWCfv7+nKRP496MkjpXaLPfp9OkgPBMR1PAhH4pgXLPJfmWHRby6QA1ixdu /HDQ== MIME-Version: 1.0 X-Received: by 10.180.210.165 with SMTP id mv5mr2762669wic.64.1440746149884; Fri, 28 Aug 2015 00:15:49 -0700 (PDT) Received: by 10.28.21.132 with HTTP; Fri, 28 Aug 2015 00:15:49 -0700 (PDT) Date: Fri, 28 Aug 2015 10:15:49 +0300 Message-ID: Subject: GIC - interrupts interpretation in DTS/FDT From: Mihai Carabas To: freebsd-arm@freebsd.org Content-Type: text/plain; charset=UTF-8 X-Content-Filtered-By: Mailman/MimeDel 2.1.20 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Aug 2015 07:15:51 -0000 Hi everyone, In the sys/arm/arm/gic.c there is a comment: "The hardware only supports active-high-level or rising-edge". From where is this deducted? I'm looking in the TRM for Cortex-A15 and there are some interrupts active-low-level. E.g.: "Virtual Timer event (PPI4) This is the event generated from the virtual timer and uses ID27. The interrupt is active-LOW level-sensitive." Thanks, Mihai