From owner-svn-src-all@freebsd.org Fri Nov 16 11:17:20 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 56543112FAF5; Fri, 16 Nov 2018 11:17:20 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C44667BA87; Fri, 16 Nov 2018 11:17:19 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A4BB11C7B9; Fri, 16 Nov 2018 11:17:19 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wAGBHJoJ033563; Fri, 16 Nov 2018 11:17:19 GMT (envelope-from sgalabov@FreeBSD.org) Received: (from sgalabov@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wAGBHIUB033559; Fri, 16 Nov 2018 11:17:18 GMT (envelope-from sgalabov@FreeBSD.org) Message-Id: <201811161117.wAGBHIUB033559@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: sgalabov set sender to sgalabov@FreeBSD.org using -f From: Stanislav Galabov Date: Fri, 16 Nov 2018 11:17:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r340476 - head/sys/mips/mediatek X-SVN-Group: head X-SVN-Commit-Author: sgalabov X-SVN-Commit-Paths: head/sys/mips/mediatek X-SVN-Commit-Revision: 340476 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: C44667BA87 X-Spamd-Result: default: False [-106.88 / 40.00]; ARC_NA(0.00)[]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; ALLOW_DOMAIN_WHITELIST(-100.00)[FreeBSD.org]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; TO_MATCH_ENVRCPT_ALL(0.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; MIME_GOOD(-0.10)[text/plain]; TO_DN_NONE(0.00)[]; HAS_XAW(0.00)[]; R_SPF_SOFTFAIL(0.00)[~all]; DMARC_NA(0.00)[FreeBSD.org]; RCVD_COUNT_THREE(0.00)[4]; MX_GOOD(-0.01)[cached: mx1.FreeBSD.org]; NEURAL_HAM_SHORT(-1.00)[-1.000,0]; FROM_EQ_ENVFROM(0.00)[]; R_DKIM_NA(0.00)[]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US]; IP_SCORE(-3.77)[ip: (-9.91), ipnet: 2610:1c1:1::/48(-4.93), asn: 11403(-3.91), country: US(-0.10)] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Nov 2018 11:17:20 -0000 Author: sgalabov Date: Fri Nov 16 11:17:18 2018 New Revision: 340476 URL: https://svnweb.freebsd.org/changeset/base/340476 Log: Implement support for sysctl hw.model for Mediatek/Ralink SoCs These SoCs have CHIPID registers, which store the Chip model, according to the manufacturer; make use of those in order to better identify the chip we're actually running on. If we're unable to read the CHIPID registers for some reason we will use the string "unknown " as a value for hw.model. Reported by: yamori813@yahoo.co.jp Sponsored by: Smartcom - Bulgaria AD Modified: head/sys/mips/mediatek/mtk_machdep.c head/sys/mips/mediatek/mtk_soc.c head/sys/mips/mediatek/mtk_soc.h head/sys/mips/mediatek/mtk_sysctl.h Modified: head/sys/mips/mediatek/mtk_machdep.c ============================================================================== --- head/sys/mips/mediatek/mtk_machdep.c Fri Nov 16 10:20:35 2018 (r340475) +++ head/sys/mips/mediatek/mtk_machdep.c Fri Nov 16 11:17:18 2018 (r340476) @@ -233,6 +233,8 @@ platform_start(__register_t a0 __unused, __register_t while (1); mtk_soc_try_early_detect(); + mtk_soc_set_cpu_model(); + if ((timer_clk = mtk_soc_get_timerclk()) == 0) timer_clk = 1000000000; /* no such speed yet */ Modified: head/sys/mips/mediatek/mtk_soc.c ============================================================================== --- head/sys/mips/mediatek/mtk_soc.c Fri Nov 16 10:20:35 2018 (r340475) +++ head/sys/mips/mediatek/mtk_soc.c Fri Nov 16 11:17:18 2018 (r340476) @@ -52,6 +52,9 @@ static uint32_t mtk_soc_uartclk = 0; static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ; static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2; +static uint32_t mtk_soc_chipid0_3 = MTK_UNKNOWN_CHIPID0_3; +static uint32_t mtk_soc_chipid4_7 = MTK_UNKNOWN_CHIPID4_7; + static const struct ofw_compat_data compat_data[] = { { "ralink,rt2880-soc", MTK_SOC_RT2880 }, { "ralink,rt3050-soc", MTK_SOC_RT3050 }, @@ -295,6 +298,10 @@ mtk_soc_try_early_detect(void) if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh)) return; + /* Get our CHIP ID */ + mtk_soc_chipid0_3 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3); + mtk_soc_chipid4_7 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID4_7); + /* First, figure out the CPU clock */ switch (mtk_soc_socid) { case MTK_SOC_RT2880: @@ -387,6 +394,28 @@ mtk_soc_try_early_detect(void) } bus_space_unmap(bst, bsh, MTK_DEFAULT_SIZE); +} + +extern char cpu_model[]; + +void +mtk_soc_set_cpu_model(void) +{ + uint32_t *p_model = (uint32_t *)cpu_model; + + /* + * CHIPID is always 2x32 bit registers, containing the ASCII + * representation of the chip, so use that directly. + * + * The info is either pre-populated in mtk_soc_try_early_detect() or + * it is left at its default value of "unknown " if it could not be + * obtained for some reason. + */ + p_model[0] = mtk_soc_chipid0_3; + p_model[1] = mtk_soc_chipid4_7; + + /* Null-terminate the string */ + cpu_model[8] = 0; } uint32_t Modified: head/sys/mips/mediatek/mtk_soc.h ============================================================================== --- head/sys/mips/mediatek/mtk_soc.h Fri Nov 16 10:20:35 2018 (r340475) +++ head/sys/mips/mediatek/mtk_soc.h Fri Nov 16 11:17:18 2018 (r340476) @@ -122,6 +122,7 @@ enum mtk_soc_id { #define MTK_DEFAULT_SIZE 0x6000 extern void mtk_soc_try_early_detect(void); +extern void mtk_soc_set_cpu_model(void); extern uint32_t mtk_soc_get_uartclk(void); extern uint32_t mtk_soc_get_cpuclk(void); extern uint32_t mtk_soc_get_timerclk(void); Modified: head/sys/mips/mediatek/mtk_sysctl.h ============================================================================== --- head/sys/mips/mediatek/mtk_sysctl.h Fri Nov 16 10:20:35 2018 (r340475) +++ head/sys/mips/mediatek/mtk_sysctl.h Fri Nov 16 11:17:18 2018 (r340476) @@ -54,6 +54,9 @@ #define RT3350_CHIPID0_3 0x33335452 +#define MTK_UNKNOWN_CHIPID0_3 0x6E6B6E75 /* "unkn" */ +#define MTK_UNKNOWN_CHIPID4_7 0x206E776F /* "own " */ + extern uint32_t mtk_sysctl_get(uint32_t); extern void mtk_sysctl_set(uint32_t, uint32_t); extern void mtk_sysctl_clr_set(uint32_t, uint32_t, uint32_t);