From owner-freebsd-threads@FreeBSD.ORG Wed Aug 6 14:12:41 2003 Return-Path: Delivered-To: freebsd-threads@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id C1ABC37B401 for ; Wed, 6 Aug 2003 14:12:41 -0700 (PDT) Received: from mail.pcnet.com (mail.pcnet.com [204.213.232.4]) by mx1.FreeBSD.org (Postfix) with ESMTP id 255F743F3F for ; Wed, 6 Aug 2003 14:12:41 -0700 (PDT) (envelope-from eischen@vigrid.com) Received: from mail.pcnet.com (mail.pcnet.com [204.213.232.4]) by mail.pcnet.com (8.12.8/8.12.1) with ESMTP id h76LCeuN020117; Wed, 6 Aug 2003 17:12:40 -0400 (EDT) Date: Wed, 6 Aug 2003 17:12:40 -0400 (EDT) From: Daniel Eischen X-Sender: eischen@pcnet5.pcnet.com To: Marcel Moolenaar In-Reply-To: <20030806205308.GA1179@athlon.pn.xcllnt.net> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII cc: threads@freebsd.org Subject: Re: KSE/ia64: a quick update X-BeenThere: freebsd-threads@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list Reply-To: deischen@freebsd.org List-Id: Threading on FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Aug 2003 21:12:42 -0000 On Wed, 6 Aug 2003, Marcel Moolenaar wrote: > On Wed, Aug 06, 2003 at 03:28:52PM -0400, Daniel Eischen wrote: > > > If you chose this route, or something similar that needs a > > system call, you might optimize the kernel. You might > > only need to make an upcall when the KSE's quantum expired > > instead of whenever a thread was interrupted. Or perhaps > > when there are no unblocked threads in the kernel that > > require an upcall to notify the UTS, there's no need > > to make an upcall. > > > > In regards to the high FPU thing. Can't you tell the > > UTS via the exported context whether a high FPU restore > > is necessary? > > It's always necessary. Even if the high FP wasn't enabled > at the time of the interrupt, it doesn't mean that the high > FP registers don't have valid values. It's just that they > haven't been accessed in that timeslice yet (we need some > heuristics to enable the high FP by default for that process > until after some timeout -- that avoids a trap every time > slice). I see. FWIW, we don't have a way to eliminate the trap on x86 either. Once the context is marked with the FPU registers being from the FPU itself or the PCB, we always restore them. The thing to realize I guess is that once you trap, you won't do it again until the FPU has been taken away again. So you may only trap the first time, and a few other times following that you may not. You can have to weigh that against always using a system call to restore the context. I'm not sure what the difference would be. > Also, another thread may use the high FP registers and since > user level threading is indistinguishable for the kernel, we > need to either have synchronous context switches or save the > whole lot for async context switches. > > I think I'll go with the following (for async contexts): > > o Use ifa and isr in the context to pass the pointer to the > mailbox and the value we want to write to it. Both are > only used by the kernel to pass information about the > fault or interrupt to the kernel, so they are unused > fields in contexts. > o Set a flag in the context to indicate that we want the > mailbox set (if applicable). > o Use the break-based syscall path to call setcontext(2). > o Have the kernel switch the context and set the mailbox. > > It's a bit of a hack, but I think other solutions are much > more painful. Both implementation-wise and kludge-wise. If there's anything more we can do, let us know. -- Dan Eischen