From owner-p4-projects@FreeBSD.ORG Sat Nov 29 18:32:03 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 71EF9106567D; Sat, 29 Nov 2008 18:32:03 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 35DD5106567B for ; Sat, 29 Nov 2008 18:32:03 +0000 (UTC) (envelope-from sam@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 1F0588FC14 for ; Sat, 29 Nov 2008 18:32:03 +0000 (UTC) (envelope-from sam@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id mATIW3NR081496 for ; Sat, 29 Nov 2008 18:32:03 GMT (envelope-from sam@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id mATIW30F081494 for perforce@freebsd.org; Sat, 29 Nov 2008 18:32:03 GMT (envelope-from sam@freebsd.org) Date: Sat, 29 Nov 2008 18:32:03 GMT Message-Id: <200811291832.mATIW30F081494@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to sam@freebsd.org using -f From: Sam Leffler To: Perforce Change Reviews Cc: Subject: PERFORCE change 153776 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 29 Nov 2008 18:32:03 -0000 http://perforce.freebsd.org/chv.cgi?CH=153776 Change 153776 by sam@sam_ebb on 2008/11/29 18:31:52 add Cambria support Affected files ... .. //depot/projects/vap/sys/arm/xscale/ixp425/avila_machdep.c#9 edit Differences ... ==== //depot/projects/vap/sys/arm/xscale/ixp425/avila_machdep.c#9 (text+ko) ==== @@ -147,105 +147,90 @@ /* Static device mappings. */ static const struct pmap_devmap ixp425_devmap[] = { /* Physical/Virtual address for I/O space */ - { - IXP425_IO_VBASE, - IXP425_IO_HWBASE, - IXP425_IO_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* Expansion Bus */ - { - IXP425_EXP_VBASE, - IXP425_EXP_HWBASE, - IXP425_EXP_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* IXP425 PCI Configuration */ - { - IXP425_PCI_VBASE, - IXP425_PCI_HWBASE, - IXP425_PCI_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* SDRAM Controller */ - { - IXP425_MCU_VBASE, - IXP425_MCU_HWBASE, - IXP425_MCU_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* PCI Memory Space */ - { - IXP425_PCI_MEM_VBASE, - IXP425_PCI_MEM_HWBASE, - IXP425_PCI_MEM_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* Q-Mgr Memory Space */ + { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* NPE-A Memory Space */ - { - IXP425_NPE_A_VBASE, - IXP425_NPE_A_HWBASE, - IXP425_NPE_A_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_NPE_A_VBASE, IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* NPE-B Memory Space */ - { - IXP425_NPE_B_VBASE, - IXP425_NPE_B_HWBASE, - IXP425_NPE_B_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_NPE_B_VBASE, IXP425_NPE_B_HWBASE, IXP425_NPE_B_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* NPE-C Memory Space */ - { - IXP425_NPE_C_VBASE, - IXP425_NPE_C_HWBASE, - IXP425_NPE_C_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_NPE_C_VBASE, IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* MAC-A Memory Space */ - { - IXP425_MAC_A_VBASE, - IXP425_MAC_A_HWBASE, - IXP425_MAC_A_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_MAC_A_VBASE, IXP425_MAC_A_HWBASE, IXP425_MAC_A_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, /* MAC-B Memory Space */ - { - IXP425_MAC_B_VBASE, - IXP425_MAC_B_HWBASE, - IXP425_MAC_B_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_MAC_B_VBASE, IXP425_MAC_B_HWBASE, IXP425_MAC_B_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + { 0 }, +}; + +/* Static device mappings. */ +static const struct pmap_devmap ixp435_devmap[] = { + /* Physical/Virtual address for I/O space */ + { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* Expansion Bus */ + { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* IXP425 PCI Configuration */ + { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* DDRII Controller NB: mapped same place as IXP425 */ + { IXP435_MCU_VBASE, IXP435_MCU_HWBASE, IXP435_MCU_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* PCI Memory Space */ + { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* Q-Mgr Memory Space */ - { - IXP425_QMGR_VBASE, - IXP425_QMGR_HWBASE, - IXP425_QMGR_SIZE, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, + { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* NPE-A Memory Space */ + { IXP425_NPE_A_VBASE, IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* NPE-C Memory Space */ + { IXP425_NPE_C_VBASE, IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + + /* MAC-C Memory Space */ + { IXP435_MAC_C_VBASE, IXP435_MAC_C_HWBASE, IXP435_MAC_C_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* MAC-A Memory Space */ + { IXP435_MAC_A_VBASE, IXP435_MAC_A_HWBASE, IXP435_MAC_A_SIZE, + VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, - { - 0, - 0, - 0, - 0, - 0, - } + { 0 } }; extern vm_offset_t xscale_cache_clean_addr; @@ -265,7 +250,7 @@ vm_offset_t lastaddr; uint32_t memsize; - set_cpufuncs(); + set_cpufuncs(); /* NB: sets cputype */ lastaddr = fake_preload_metadata(); pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); @@ -400,7 +385,10 @@ /* Map the vector page. */ pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_devmap_bootstrap(l1pagetable, ixp425_devmap); + if (cpu_is_ixp43x()) + pmap_devmap_bootstrap(l1pagetable, ixp435_devmap); + else + pmap_devmap_bootstrap(l1pagetable, ixp425_devmap); /* * Give the XScale global cache clean code an appropriately * sized chunk of unmapped VA space starting at 0xff000000 @@ -436,12 +424,16 @@ * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + /* ready to setup the console (XXX move earlier if possible) */ + cninit(); /* - * Fetch the SDRAM start/size from the ixp425 SDRAM configration - * registers. + * Fetch the RAM size from the MCU registers. The + * expansion bus was mapped above so we can now read 'em. */ - cninit(); - memsize = ixp425_sdram_size(); + if (cpu_is_ixp43x()) + memsize = ixp435_ddram_size(); + else + memsize = ixp425_sdram_size(); physmem = memsize / PAGE_SIZE; /* Set stack for exception handlers */