Date: Mon, 2 May 2022 17:37:11 GMT From: Kevin Bowling <kbowling@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: cfac74ea1224 - main - cad/iverilog: Take maintainer Message-ID: <202205021737.242HbBcl019160@gitrepo.freebsd.org>
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The branch main has been updated by kbowling: URL: https://cgit.FreeBSD.org/ports/commit/?id=cfac74ea122408b0bd6baec80e6bdce880a42bad commit cfac74ea122408b0bd6baec80e6bdce880a42bad Author: Kevin Bowling <kbowling@FreeBSD.org> AuthorDate: 2022-05-02 17:29:45 +0000 Commit: Kevin Bowling <kbowling@FreeBSD.org> CommitDate: 2022-05-02 17:29:45 +0000 cad/iverilog: Take maintainer --- cad/iverilog/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index 741eb3fdd9c4..3b8aba2764b7 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -6,7 +6,7 @@ CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/ DISTNAME= verilog-${PORTVERSION} -MAINTAINER= ports@FreeBSD.org +MAINTAINER= kbowling@FreeBSD.org COMMENT= Verilog simulation and synthesis tool LICENSE= GPLv2
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