Date: Thu, 09 Apr 2015 03:17:01 -0500 From: Alan Cox <alc@rice.edu> To: Mateusz Guzik <mjguzik@gmail.com>, freebsd-arch@freebsd.org Cc: Attilio Rao <attilio@FreeBSD.org>, adrian@freebsd.org, Konstantin Belousov <kib@FreeBSD.org> Subject: Re: atomic ops Message-ID: <5526357D.3080403@rice.edu> In-Reply-To: <20150409061448.GB6086@dft-labs.eu> References: <20141028025222.GA19223@dft-labs.eu> <20150409061448.GB6086@dft-labs.eu>
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On 04/09/2015 01:14, Mateusz Guzik wrote: > On Tue, Oct 28, 2014 at 03:52:22AM +0100, Mateusz Guzik wrote: > [scratching old content so that I hopefully re-state it nicer] > > I would like to reviwe the discussion about memory barriers provided in= > the kernel. > > The kernel (at least on amd64) lacks lightweight barriers providing onl= y > following guarantees: > - all writes are completed prior to given point > - all reads are completed prior to given point > > On amd64 such barriers require only compiler barrier, and as such > obviously beat currently used operations like load_acq (which uses > cmpxchg). > > Example consumer which would benefit greatly from such barriers is > seq.h: > https://svnweb.freebsd.org/base/head/sys/sys/seq.h?view=3Dmarkup > > _load_acq on amd64 provides full barrier and it was noted we should not= > change that in order to not break possible 3rd party consumers. > Also I don't see any alternative naming convention trying to stick to > this scheme that we could use. > > As such I propose stealing naming from Linux and introduction of smp_wm= b > and smp_rmb macros providing aforementioned funcionality. > > So for amd64 this would be: > #define smp_wmb() __compiler_membar() > #define smp_rmb() __compiler_membar() > > Any objections? > > I'm happy to talk to arch maintainers in order to get relevant > implementations for all architectures. > How about stealing from C11's stdatomic.h instead of Linux. C11's model for expressing memory access ordering requirements is, like our atomic.h, inspired by the release consistency model. And, stdatomic.h has an operation, atomic_thread_fence(), that allows you to express the need for acquire and/or release ordering at some point in your program without an associated memory access.
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