Date: Mon, 12 Nov 2012 01:35:52 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 219753 for review Message-ID: <201211120135.qAC1Zqx8039124@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@219753?ac=10 Change 219753 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2012/11/12 01:35:02 Implement CHERI_CLW() C-language macro around CHERI CLW instruction. Annotate that we're not able to use immediates due to assembler limitations here, and above where we also have store-related CHERI instructions. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#13 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#13 (text+ko) ==== @@ -163,6 +163,8 @@ /* * Data stores; while these don't muck with c0, they do require memory * clobbers. + * + * XXXRW: immediates not yet supported by the assembler. */ #define CHERI_CSB(rs, rt, offset, cb) do { \ __asm__ __volatile__ ("csb %0, %1($c%2)" : : \ @@ -185,6 +187,17 @@ } while (0) /* + * Data loads: while these don't much with c0, they do require memory + * clobbers. + * + * XXXRW: immediates not yet supported by the assembler. + */ +#define CHERI_CLW(rd, rt, offset, cb) do { \ + __asm__ __volatile__ ("clw %0, %1($c%2)" : \ + "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ +} while (0) + +/* * Routines that modify or replace values in capability registers, and that if * if used on C0, require the compiler to write registers back to memory, and * reload afterwards, since we may effectively be changing the compiler-
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