Date: Sun, 28 May 2017 07:44:55 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r319055 - head/sys/mips/atheros Message-ID: <201705280744.v4S7it5j071688@repo.freebsd.org>
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Author: adrian Date: Sun May 28 07:44:55 2017 New Revision: 319055 URL: https://svnweb.freebsd.org/changeset/base/319055 Log: [ar71xx] undo read-after-write to flush; some bus devices dislike this. This broke the PCI fixup on at least the AR7240 + AR9280 reference design board that I have. Tested: * Atheros AP93 reference design - AR7240 + AR9280 Modified: head/sys/mips/atheros/ar71xxreg.h Modified: head/sys/mips/atheros/ar71xxreg.h ============================================================================== --- head/sys/mips/atheros/ar71xxreg.h Sun May 28 07:40:42 2017 (r319054) +++ head/sys/mips/atheros/ar71xxreg.h Sun May 28 07:44:55 2017 (r319055) @@ -528,13 +528,14 @@ typedef enum { #define AR71XX_SPI_RDS 0x0C #define ATH_READ_REG(reg) \ - *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) - + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) +/* + * Note: Don't put a flush read here; some users (eg the AR724x PCI fixup code) + * requires write-only space to certain registers. Doing the read afterwards + * causes things to break. + */ #define ATH_WRITE_REG(reg, val) \ - do { \ - *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val); \ - (void) ATH_READ_REG(reg); \ - } while (0) + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val) static inline void ar71xx_ddr_flush(uint32_t reg)
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