Date: Sat, 6 May 2023 17:49:43 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 7253dc57a0b4 - main - hwpmc: formatting of CPU and class lists Message-ID: <202305061749.346HnhDd017909@gitrepo.freebsd.org>
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The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=7253dc57a0b400ff745a43017928304ff8dcf33f commit 7253dc57a0b400ff745a43017928304ff8dcf33f Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2023-05-05 21:58:13 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2023-05-06 17:49:19 +0000 hwpmc: formatting of CPU and class lists The end result is much more legible in both cases. Reviewed by: jkoshy MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D39906 --- sys/sys/pmc.h | 126 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 62 insertions(+), 64 deletions(-) diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index 6a9f614bcbc8..558fe4b20d39 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -82,50 +82,49 @@ extern char pmc_cpuid[PMC_CPUID_LEN]; * * Please keep the pmc(3) manual page in sync with this list. */ - -#define __PMC_CPUS() \ - __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ - __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ - __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ - __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ - __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ - __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ - __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ - __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ - __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ - __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ - __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ - __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ - __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ - __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ - __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ - __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ - __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ - __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ - __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ - __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ - __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ - __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ - __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ - __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ - __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ - __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ - __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ - __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ - __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ - __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ - __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ - __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ - __PMC_CPU(GENERIC, 0x400, "Generic") \ - __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ - __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ - __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ - __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ - __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ - __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ - __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ - __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ - __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") +#define __PMC_CPUS() \ + __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ + __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ + __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ + __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ + __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ + __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ + __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ + __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ + __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ + __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ + __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ + __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ + __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ + __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ + __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ + __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ + __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ + __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ + __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ + __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ + __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ + __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ + __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ + __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ + __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ + __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ + __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ + __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ + __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ + __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ + __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ + __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ + __PMC_CPU(GENERIC, 0x400, "Generic") \ + __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ + __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ + __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ + __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ + __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ + __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ + __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ + __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ + __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") enum pmc_cputype { #undef __PMC_CPU @@ -139,26 +138,25 @@ enum pmc_cputype { /* * Classes of PMCs */ - -#define __PMC_CLASSES() \ - __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ - __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ - __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ - __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ - __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ - __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ - __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ - __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ - __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ - __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ - __PMC_CLASS(SOFT, 0x0F, "Software events") \ - __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ - __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ - __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ - __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ - __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \ - __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \ - __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU") +#define __PMC_CLASSES() \ + __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ + __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ + __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ + __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ + __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ + __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ + __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ + __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ + __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ + __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ + __PMC_CLASS(SOFT, 0x0F, "Software events") \ + __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ + __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ + __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ + __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ + __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \ + __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \ + __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU") enum pmc_class { #undef __PMC_CLASS
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