Date: Sat, 29 Nov 2008 18:42:13 GMT From: Sam Leffler <sam@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 153778 for review Message-ID: <200811291842.mATIgDdn082257@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=153778 Change 153778 by sam@sam_ebb on 2008/11/29 18:41:30 add ixp435 and Cambria-specific definitions Affected files ... .. //depot/projects/vap/sys/arm/xscale/ixp425/ixp425reg.h#3 edit Differences ... ==== //depot/projects/vap/sys/arm/xscale/ixp425/ixp425reg.h#3 (text+ko) ==== @@ -64,7 +64,7 @@ * * 4000 0000 --------------------------- * SDRAM - * 1000 0000 --------------------------- + * 0000 0000 --------------------------- */ /* @@ -115,6 +115,11 @@ #define IXP425_MAC_B_OFFSET 0x0000a000UL #define IXP425_USB_OFFSET 0x0000b000UL +#define IXP435_MAC_C_OFFSET 0x0000a000UL /* Ethernet MAC on NPE C */ +#define IXP435_MAC_A_OFFSET 0x0000c000UL /* Ethernet MAC on NPE A */ +#define IXP435_USB1_OFFSET 0x0000d000UL /* USB host controller 1 */ +#define IXP435_USB2_OFFSET 0x0000e000UL /* USB host controller 2 */ + #define IXP425_REG_SIZE 0x1000 /* @@ -224,6 +229,18 @@ #define IXP425_INT_NPE_B 1 /* NPE B */ #define IXP425_INT_NPE_A 0 /* NPE A */ +/* NB: IXP435 has an additional 32 IRQ's */ +#define IXP435_INT_STATUS2 (IXP425_IRQ_VBASE + 0x20) +#define IXP435_INT_ENABLE2 (IXP425_IRQ_VBASE + 0x24) +#define IXP435_INT_SELECT2 (IXP425_IRQ_VBASE + 0x28) +#define IXP435_IRQ_STATUS2 (IXP425_IRQ_VBASE + 0x2C) +#define IXP435_FIQ_STATUS2 (IXP425_IRQ_VBASE + 0x30) + +#define IXP435_INT_USB0 32 /* USB Host 2.0 Host 0 */ +#define IXP435_INT_USB1 33 /* USB Host 2.0 Host 1 */ +#define IXP435_INT_QMGR_PER 60 /* Queue manager parity error */ +#define IXP435_INT_ECC 61 /* Single or multi-bit ECC error */ + /* * software interrupt */ @@ -239,6 +256,11 @@ (1 << IXP425_INT_bit11))) #define IXP425_INT_GPIOMASK (0x3ff800c0u) +#define IXP435_INT_HWMASK ((1 << (IXP435_INT_USB0 - 32)) | \ + (1 << (IXP435_INT_USB1 - 32)) | \ + (1 << (IXP435_INT_QMGR_PER - 32)) | \ + (1 << (IXP435_INT_ECC - 32))) + /* * GPIO */ @@ -491,6 +513,30 @@ #define MCU_SDR_IR 0x08 /* + * IXP435 DDR MCU Registers + */ +#define IXP435_MCU_HWBASE 0xcc00e500UL +#define IXP435_MCU_VBASE 0xf0200000UL /* NB: use same addr as 425 */ +#define IXP435_MCU_SIZE 0x1000 /* NB: does not map all regs */ +#define MCU_DDR_SDIR 0x00 /* DDR SDAM Initialization Reg*/ +#define MCU_DDR_SDCR0 0x04 /* DDR SDRAM Control Reg 0 */ +#define MCU_DDR_SDCR1 0x08 /* DDR SDRAM Control Reg 1 */ +#define MCU_DDR_SDBR 0x0c /* SDRAM Base Register */ +#define MCU_DDR_SBR0 0x10 /* SDRAM Boundary Register 0 */ +#define MCU_DDR_SBR1 0x14 /* SDRAM Boundary Register 1 */ +#define MCU_DDR_ECCR 0x1c /* ECC Control Register */ +#define MCU_DDR_ELOG0 0x20 /* ECC Log Register 0 */ +#define MCU_DDR_ELOG1 0x24 /* ECC Log Register 1 */ +#define MCU_DDR_ECAR0 0x28 /* ECC Address Register 0 */ +#define MCU_DDR_ECAR1 0x2c /* ECC Address Register 1 */ +#define MCU_DDR_ECTST 0x30 /* ECC Test Register */ +#define MCU_DDR_MCISR 0x34 /* MC Interrupt Status Reg */ +#define MCU_DDR_MPTCR 0x3c /* MC Port Transaction Cnt Reg*/ +#define MCU_DDR_RFR 0x48 /* Refresh Frequency Register */ +#define MCU_DDR_SDPR(n) (0x50+(n)*4) /* SDRAM Page Register 0-7 */ +/* NB: RCVDLY at 0x1050 and LEGOVERIDE at 0x1074 */ + +/* * Performance Monitoring Unit (CP14) * * CP14.0.1 Performance Monitor Control Register(PMNC) @@ -557,6 +603,14 @@ #define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET) #define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */ +#define IXP435_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP435_MAC_A_OFFSET) +#define IXP435_MAC_A_VBASE (IXP425_IO_VBASE + IXP435_MAC_A_OFFSET) +#define IXP435_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */ + +#define IXP435_MAC_C_HWBASE (IXP425_IO_HWBASE + IXP435_MAC_C_OFFSET) +#define IXP435_MAC_C_VBASE (IXP425_IO_VBASE + IXP435_MAC_C_OFFSET) +#define IXP435_MAC_C_SIZE 0x1000 /* Actually only 256 bytes */ + /* * Expansion Bus Data Space. */ @@ -588,4 +642,25 @@ #define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6) #define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7) +/* + * IXP435/Gateworks Cambria + * + * Octal status LED latch is in upper 256K of CS3 + * Optional RS485 Serial port is next lower 256K + * Optional GPS Serial port is next lower 256K + * next lower 768K is reserved + * Compact flash socket 1 is next lower 256K + * Compact flash socket 0 is next lower 256K + */ +#define CAMBRIA_OCTAL_LED_HWBASE (IXP425_EXP_BUS_CS4_HWBASE - 0x40000) +#define CAMBRIA_OCTAL_LED_SIZE 0x40000 +#define CAMBRIA_RS485_HWBASE (CAMBRIA_OCTAL_LED_HWBASE - 0x40000) +#define CAMBRIA_RS485_SIZE 0x40000 +#define CAMBRIA_GPS_HWBASE (CAMBRIA_RS485_HWBASE - 0x40000) +#define CAMBRIA_GPS_SIZE 0x40000 +#define CAMBRIA_CFSEL1_HWBASE (CAMBRIA_GPS_HWBASE - 4*0x40000) +#define CAMBRIA_CFSEL1_SIZE 0x40000 +#define CAMBRIA_CFSEL0_HWBASE (CAMBRIA_CFSEL1_HWBASE - 0x40000) +#define CAMBRIA_CFSEL0_SIZE 0x40000 + #endif /* _IXP425REG_H_ */
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