Date: Sun, 18 Apr 2010 04:10:47 +0530 From: "C. Jayachandran" <c.jayachandran@gmail.com> To: Randall Stewart <rrs@lakerest.net> Cc: freebsd-mips@freebsd.org Subject: SMP support for XLR processors. Message-ID: <w2z98a59be81004171540t2f0d5193nca2ec9e2540502e2@mail.gmail.com>
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--001636b2be3f405cb90484766b03 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable I've a set of initial patches to enable SMP for RMI processors. It comes up in multi-user with 32 CPUs. =A0I could do buildworld before I updated to HEAD - with head there is a hang during buildworld which I'm looking at, but I think the initial work can be checked in. Neel, can you have a look at the first two patches - one is to enable ULE scheduler and the second one is to move platform_init_ap to slightly later in the initialization sequence. The patches are : 1. mips-ule-support.patch - Enable ULE scheduler for MIPS 2. mips-smp-move-platform.patch - We need a hook to setup message ring and its interrupts, we use platform_init_ap now, and move it be called later for XLR 3. rmi-prid.patch Add RMI processor ID prints - right now it prints unknown processor. 4. rmi-pcib-fix.patch XLR pci bridge should be off the IODI bus, currently it is off the nexus bus which will cause issue when bus_setup_intr on nexus is called 5. cleanup-reorg-cpuid-rge-kx.patch This set has a many changes rolled up: =A0- clean up rge driver, remove unused code paths and commented code (long way to go still) =A0- xlr_cpu_id(), xlr_core_id() and xlr_thr_id() updated and usage updated =A0- fix a bug - we cannot use MIPS_PHYS_TO_KSEG0 on physical addresses here, I have made changes for using XKPHYS to do the same process. =A0- the KX bit is enabled and interrupts are disabled before the physical memory is read, to avoid the KX bit setting from affecting other code. - move message ring code to on_chip.c from xlr_machdep.c, now all message ring code is in on_chip.c 6. rmi-xlr-smp.patch SMP Support for XLR - mpwait.S added to get the other CPUs out of bootloader code at startup. - SMP platform related functions. - disable shared TLB code for SMP - since threads have different mappings. The patches are also available at http://sites.google.com/site/cjayachandran/files Enabling all 32 threads will need a minor fix in the SMP code, see the patch subr_smp-fix.patch at the same place. Regards, JC. --001636b2be3f405cb90484766b03 Content-Type: application/octet-stream; name="mips-ule-support.patch" Content-Disposition: attachment; filename="mips-ule-support.patch" Content-Transfer-Encoding: base64 X-Attachment-Id: f_g8503ozq0 SW5kZXg6IHN5cy9rZXJuL3NjaGVkX3VsZS5jCj09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KLS0tIHN5cy9rZXJuL3NjaGVk X3VsZS5jCShyZXZpc2lvbiAyMDY3MzUpCisrKyBzeXMva2Vybi9zY2hlZF91bGUuYwkod29ya2lu ZyBjb3B5KQpAQCAtODAsNyArODAsNyBAQAogI2luY2x1ZGUgPG1hY2hpbmUvY3B1Lmg+CiAjaW5j bHVkZSA8bWFjaGluZS9zbXAuaD4KIAotI2lmIGRlZmluZWQoX19zcGFyYzY0X18pIHx8IGRlZmlu ZWQoX19taXBzX18pCisjaWYgZGVmaW5lZChfX3NwYXJjNjRfXykKICNlcnJvciAiVGhpcyBhcmNo aXRlY3R1cmUgaXMgbm90IGN1cnJlbnRseSBjb21wYXRpYmxlIHdpdGggVUxFIgogI2VuZGlmCiAK SW5kZXg6IHN5cy9taXBzL2luY2x1ZGUvc21wLmgKPT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PQotLS0gc3lzL21pcHMvaW5j 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