Date: Fri, 30 Oct 2015 23:00:48 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r290212 - head/sys/mips/atheros Message-ID: <201510302300.t9UN0m76098207@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: adrian Date: Fri Oct 30 23:00:47 2015 New Revision: 290212 URL: https://svnweb.freebsd.org/changeset/base/290212 Log: arge_mdio: add explicit read barriers for MDIO_READs. The mips74k programmers guide notes that reads can be re-ordered, even uncached ones, so we need an explicit SYNC between them. Yes, this is a case of a driver author actively doing a bus barrier operation. This ends up being necessary when the mips74k core is run in write-back mode rather than write-through mode. That's coming in an upcoming commit. Tested: * mips74k, QCA9558 SoC (AP135 reference board), arge<->arge interface routing traffic tests. Modified: head/sys/mips/atheros/if_arge.c Modified: head/sys/mips/atheros/if_arge.c ============================================================================== --- head/sys/mips/atheros/if_arge.c Fri Oct 30 22:55:41 2015 (r290211) +++ head/sys/mips/atheros/if_arge.c Fri Oct 30 23:00:47 2015 (r290212) @@ -1081,8 +1081,10 @@ arge_miibus_readreg(device_t dev, int ph i = ARGE_MII_TIMEOUT; while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) & - MAC_MII_INDICATOR_BUSY) && (i--)) + MAC_MII_INDICATOR_BUSY) && (i--)) { + ARGE_MDIO_BARRIER_READ(sc); DELAY(5); + } if (i < 0) { mtx_unlock(&miibus_mtx); @@ -1092,6 +1094,7 @@ arge_miibus_readreg(device_t dev, int ph } result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; + ARGE_MDIO_BARRIER_READ(sc); ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); mtx_unlock(&miibus_mtx); @@ -1119,8 +1122,10 @@ arge_miibus_writereg(device_t dev, int p i = ARGE_MII_TIMEOUT; while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) & - MAC_MII_INDICATOR_BUSY) && (i--)) + MAC_MII_INDICATOR_BUSY) && (i--)) { + ARGE_MDIO_BARRIER_READ(sc); DELAY(5); + } mtx_unlock(&miibus_mtx);
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201510302300.t9UN0m76098207>