From owner-svn-src-all@freebsd.org Wed Feb 1 21:34:52 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 423A2CCCDDE; Wed, 1 Feb 2017 21:34:52 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id ECAA7C0D; Wed, 1 Feb 2017 21:34:51 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v11LYpub099774; Wed, 1 Feb 2017 21:34:51 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v11LYl2C099741; Wed, 1 Feb 2017 21:34:47 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201702012134.v11LYl2C099741@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 1 Feb 2017 21:34:47 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r313056 - in vendor/llvm/dist: cmake/modules include/llvm/CodeGen lib/CodeGen lib/CodeGen/AsmPrinter lib/CodeGen/SelectionDAG lib/MC lib/Target/Mips lib/Target/Mips/AsmParser lib/Target... X-SVN-Group: vendor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Feb 2017 21:34:52 -0000 Author: dim Date: Wed Feb 1 21:34:47 2017 New Revision: 313056 URL: https://svnweb.freebsd.org/changeset/base/313056 Log: Vendor import of llvm release_40 branch r293807: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293807 Added: vendor/llvm/dist/test/CodeGen/SystemZ/pr31710.ll vendor/llvm/dist/test/DebugInfo/Mips/tls.ll vendor/llvm/dist/test/MC/MachO/ARM/no-tls-assert.ll vendor/llvm/dist/test/Transforms/IPConstantProp/naked-return.ll vendor/llvm/dist/test/Transforms/InterleavedAccess/AArch64/ vendor/llvm/dist/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user.ll vendor/llvm/dist/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll vendor/llvm/dist/test/Transforms/InterleavedAccess/AArch64/lit.local.cfg vendor/llvm/dist/test/Transforms/InterleavedAccess/ARM/ vendor/llvm/dist/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user.ll vendor/llvm/dist/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll vendor/llvm/dist/test/Transforms/InterleavedAccess/ARM/lit.local.cfg Deleted: vendor/llvm/dist/test/CodeGen/AArch64/aarch64-interleaved-accesses-extract-user.ll vendor/llvm/dist/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll vendor/llvm/dist/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll vendor/llvm/dist/test/CodeGen/ARM/arm-interleaved-accesses.ll vendor/llvm/dist/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt vendor/llvm/dist/test/MC/Mips/mips3/invalid-mips4-wrong-error.s Modified: vendor/llvm/dist/cmake/modules/DetermineGCCCompatible.cmake vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGISel.h vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/DIE.cpp vendor/llvm/dist/lib/CodeGen/InterleavedAccessPass.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp vendor/llvm/dist/lib/MC/MCMachOStreamer.cpp vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFPU.td vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFormats.td vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.cpp vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.h vendor/llvm/dist/lib/Target/Mips/MipsFastISel.cpp vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td vendor/llvm/dist/lib/Target/Mips/MipsInstrFormats.td vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.cpp vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.h vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.td vendor/llvm/dist/lib/Target/PowerPC/PPCSchedule.td vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE500mc.td vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE5500.td vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp vendor/llvm/dist/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt vendor/llvm/dist/test/MC/Mips/micromips/valid.s vendor/llvm/dist/test/MC/Mips/mips1/invalid-mips4-wrong-error.s vendor/llvm/dist/test/MC/Mips/mips1/invalid-mips4.s vendor/llvm/dist/test/MC/Mips/mips1/invalid-mips5-wrong-error.s vendor/llvm/dist/test/MC/Mips/mips1/invalid-mips5.s vendor/llvm/dist/test/MC/Mips/mips2/invalid-mips32.s vendor/llvm/dist/test/MC/Mips/mips2/invalid-mips32r2.s vendor/llvm/dist/test/MC/Mips/mips2/invalid-mips4-wrong-error.s vendor/llvm/dist/test/MC/Mips/mips2/invalid-mips4.s vendor/llvm/dist/test/MC/Mips/mips2/invalid-mips5.s vendor/llvm/dist/test/MC/Mips/mips3/invalid-mips4.s vendor/llvm/dist/test/MC/Mips/mips3/invalid-mips5-wrong-error.s vendor/llvm/dist/test/MC/Mips/mips3/invalid-mips5.s vendor/llvm/dist/test/MC/Mips/mips32/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips32/valid.s vendor/llvm/dist/test/MC/Mips/mips32r2/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips32r2/valid.s vendor/llvm/dist/test/MC/Mips/mips32r3/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips32r3/valid.s vendor/llvm/dist/test/MC/Mips/mips32r5/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips32r5/valid.s vendor/llvm/dist/test/MC/Mips/mips4/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips4/valid.s vendor/llvm/dist/test/MC/Mips/mips5/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips5/valid.s vendor/llvm/dist/test/MC/Mips/mips64/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips64/valid.s vendor/llvm/dist/test/MC/Mips/mips64r2/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips64r2/valid.s vendor/llvm/dist/test/MC/Mips/mips64r3/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips64r3/valid.s vendor/llvm/dist/test/MC/Mips/mips64r5/valid-xfail.s vendor/llvm/dist/test/MC/Mips/mips64r5/valid.s vendor/llvm/dist/test/MC/PowerPC/ppc64-encoding-bookIII.s vendor/llvm/dist/test/Transforms/InstCombine/indexed-gep-compares.ll vendor/llvm/dist/test/Transforms/InstCombine/load.ll vendor/llvm/dist/test/tools/llvm-symbolizer/coff-exports.test Modified: vendor/llvm/dist/cmake/modules/DetermineGCCCompatible.cmake ============================================================================== --- vendor/llvm/dist/cmake/modules/DetermineGCCCompatible.cmake Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/cmake/modules/DetermineGCCCompatible.cmake Wed Feb 1 21:34:47 2017 (r313056) @@ -7,5 +7,7 @@ if(NOT DEFINED LLVM_COMPILER_IS_GCC_COMP set(LLVM_COMPILER_IS_GCC_COMPATIBLE OFF) elseif( "${CMAKE_CXX_COMPILER_ID}" MATCHES "Clang" ) set(LLVM_COMPILER_IS_GCC_COMPATIBLE ON) + elseif( "${CMAKE_CXX_COMPILER_ID}" MATCHES "Intel" ) + set(LLVM_COMPILER_IS_GCC_COMPATIBLE ON) endif() endif() Modified: vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h Wed Feb 1 21:34:47 2017 (r313056) @@ -480,6 +480,12 @@ public: /// Get the value for DW_AT_APPLE_isa. Zero if no isa encoding specified. virtual unsigned getISAEncoding() { return 0; } + /// Emit the directive and value for debug thread local expression + /// + /// \p Value - The value to emit. + /// \p Size - The size of the integer (in bytes) to emit. + virtual void EmitDebugValue(const MCExpr *Value, unsigned Size) const; + //===------------------------------------------------------------------===// // Dwarf Lowering Routines //===------------------------------------------------------------------===// Modified: vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGISel.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGISel.h Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGISel.h Wed Feb 1 21:34:47 2017 (r313056) @@ -305,7 +305,7 @@ private: std::vector OpcodeOffset; void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, - const SmallVectorImpl &ChainNodesMatched, + SmallVectorImpl &ChainNodesMatched, bool isMorphNodeTo); }; Modified: vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -567,6 +567,15 @@ void AsmPrinter::EmitGlobalVariable(cons OutStreamer->AddBlankLine(); } +/// Emit the directive and value for debug thread local expression +/// +/// \p Value - The value to emit. +/// \p Size - The size of the integer (in bytes) to emit. +void AsmPrinter::EmitDebugValue(const MCExpr *Value, + unsigned Size) const { + OutStreamer->EmitValue(Value, Size); +} + /// EmitFunctionHeader - This method emits the header for the current /// function. void AsmPrinter::EmitFunctionHeader() { Modified: vendor/llvm/dist/lib/CodeGen/AsmPrinter/DIE.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/AsmPrinter/DIE.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/CodeGen/AsmPrinter/DIE.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -484,7 +484,7 @@ void DIEInteger::print(raw_ostream &O) c /// EmitValue - Emit expression value. /// void DIEExpr::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { - AP->OutStreamer->EmitValue(Expr, SizeOf(AP, Form)); + AP->EmitDebugValue(Expr, SizeOf(AP, Form)); } /// SizeOf - Determine size of expression value in bytes. Modified: vendor/llvm/dist/lib/CodeGen/InterleavedAccessPass.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/InterleavedAccessPass.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/CodeGen/InterleavedAccessPass.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -174,7 +174,7 @@ static bool isDeInterleaveMask(ArrayRef< /// I.e. <0, LaneLen, ... , LaneLen*(Factor - 1), 1, LaneLen + 1, ...> /// E.g. For a Factor of 2 (LaneLen=4): <0, 4, 1, 5, 2, 6, 3, 7> static bool isReInterleaveMask(ArrayRef Mask, unsigned &Factor, - unsigned MaxFactor) { + unsigned MaxFactor, unsigned OpNumElts) { unsigned NumElts = Mask.size(); if (NumElts < 4) return false; @@ -246,6 +246,9 @@ static bool isReInterleaveMask(ArrayRef< if (StartMask < 0) break; + // We must stay within the vectors; This case can happen with undefs. + if (StartMask + LaneLen > OpNumElts*2) + break; } // Found an interleaved mask of current factor. @@ -406,7 +409,8 @@ bool InterleavedAccess::lowerInterleaved // Check if the shufflevector is RE-interleave shuffle. unsigned Factor; - if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor)) + unsigned OpNumElts = SVI->getOperand(0)->getType()->getVectorNumElements(); + if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor, OpNumElts)) return false; DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n"); Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -2248,7 +2248,7 @@ GetVBR(uint64_t Val, const unsigned char /// to use the new results. void SelectionDAGISel::UpdateChains( SDNode *NodeToMatch, SDValue InputChain, - const SmallVectorImpl &ChainNodesMatched, bool isMorphNodeTo) { + SmallVectorImpl &ChainNodesMatched, bool isMorphNodeTo) { SmallVector NowDeadNodes; // Now that all the normal results are replaced, we replace the chain and @@ -2260,6 +2260,11 @@ void SelectionDAGISel::UpdateChains( // Replace all the chain results with the final chain we ended up with. for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { SDNode *ChainNode = ChainNodesMatched[i]; + // If ChainNode is null, it's because we replaced it on a previous + // iteration and we cleared it out of the map. Just skip it. + if (!ChainNode) + continue; + assert(ChainNode->getOpcode() != ISD::DELETED_NODE && "Deleted node left in chain"); @@ -2272,6 +2277,11 @@ void SelectionDAGISel::UpdateChains( if (ChainVal.getValueType() == MVT::Glue) ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); + SelectionDAG::DAGNodeDeletedListener NDL( + *CurDAG, [&](SDNode *N, SDNode *E) { + std::replace(ChainNodesMatched.begin(), ChainNodesMatched.end(), N, + static_cast(nullptr)); + }); CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); // If the node became dead and we haven't already seen it, delete it. Modified: vendor/llvm/dist/lib/MC/MCMachOStreamer.cpp ============================================================================== --- vendor/llvm/dist/lib/MC/MCMachOStreamer.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/MC/MCMachOStreamer.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -142,7 +142,8 @@ static bool canGoAfterDWARF(const MCSect if (SegName == "__TEXT" && SecName == "__eh_frame") return true; - if (SegName == "__DATA" && SecName == "__nl_symbol_ptr") + if (SegName == "__DATA" && (SecName == "__nl_symbol_ptr" || + SecName == "__thread_ptr")) return true; return false; Modified: vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -413,6 +413,7 @@ public: Match_RequiresDifferentOperands, Match_RequiresNoZeroRegister, Match_RequiresSameSrcAndDst, + Match_NoFCCRegisterForCurrentISA, Match_NonZeroOperandForSync, #define GET_OPERAND_DIAGNOSTIC_TYPES #include "MipsGenAsmMatcher.inc" @@ -1461,8 +1462,6 @@ public: bool isFCCAsmReg() const { if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC)) return false; - if (!AsmParser.hasEightFccRegisters()) - return RegIdx.Index == 0; return RegIdx.Index <= 7; } bool isACCAsmReg() const { @@ -4053,6 +4052,7 @@ MipsAsmParser::checkEarlyTargetMatchPred return Match_RequiresSameSrcAndDst; } } + unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { switch (Inst.getOpcode()) { // As described by the MIPSR6 spec, daui must not use the zero operand for @@ -4131,9 +4131,15 @@ unsigned MipsAsmParser::checkTargetMatch if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) return Match_RequiresDifferentOperands; return Match_Success; - default: - return Match_Success; } + + uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags; + if ((TSFlags & MipsII::HasFCCRegOperand) && + (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) + return Match_NoFCCRegisterForCurrentISA; + + return Match_Success; + } static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, @@ -4191,6 +4197,9 @@ bool MipsAsmParser::MatchAndEmitInstruct return Error(IDLoc, "invalid operand ($zero) for instruction"); case Match_RequiresSameSrcAndDst: return Error(IDLoc, "source and destination must match"); + case Match_NoFCCRegisterForCurrentISA: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "non-zero fcc register doesn't exist in current ISA level"); case Match_Immz: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); case Match_UImm1_0: Modified: vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Wed Feb 1 21:34:47 2017 (r313056) @@ -123,7 +123,9 @@ namespace MipsII { HasForbiddenSlot = 1 << 5, /// IsPCRelativeLoad - A Load instruction with implicit source register /// ($pc) with explicit offset and destination register - IsPCRelativeLoad = 1 << 6 + IsPCRelativeLoad = 1 << 6, + /// HasFCCRegOperand - Instruction uses an $fcc register. + HasFCCRegOperand = 1 << 7 }; } Modified: vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFPU.td ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFPU.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFPU.td Wed Feb 1 21:34:47 2017 (r313056) @@ -27,9 +27,20 @@ def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6; def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, - CEQS_FM_MM<0>; + CEQS_FM_MM<0> { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} + def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, - CEQS_FM_MM<1>; + CEQS_FM_MM<1> { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; @@ -164,6 +175,98 @@ let AdditionalPredicates = [InMicroMips] def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, LW_FM_MM<0x26>; } + + multiclass C_COND_MM fmt, + InstrItinClass itin> { + def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.f."#NAME; + let isCommutable = 1; + } + def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.un."#NAME; + let isCommutable = 1; + } + def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.eq."#NAME; + let isCommutable = 1; + } + def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ueq."#NAME; + let isCommutable = 1; + } + def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.olt."#NAME; + } + def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ult."#NAME; + } + def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ole."#NAME; + } + def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ule."#NAME; + } + def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.sf."#NAME; + let isCommutable = 1; + } + def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ngle."#NAME; + } + def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.seq."#NAME; + let isCommutable = 1; + } + def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ngl."#NAME; + } + def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.lt."#NAME; + } + def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.nge."#NAME; + } + def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.le."#NAME; + } + def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM_MM { + let BaseOpcode = "c.ngt."#NAME; + } + } + + defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, + ISA_MIPS1_NOT_32R6_64R6; + defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + let DecoderNamespace = "Mips64" in + defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6; + defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm : BC1_ALIASES, + ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; } //===----------------------------------------------------------------------===// Modified: vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFormats.td ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFormats.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MicroMipsInstrFormats.td Wed Feb 1 21:34:47 2017 (r313056) @@ -766,6 +766,7 @@ class SWXC1_FM_MM funct> : MMArc class CEQS_FM_MM fmt> : MMArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -773,13 +774,17 @@ class CEQS_FM_MM fmt> : MMArch { let Inst{31-26} = 0x15; let Inst{25-21} = ft; let Inst{20-16} = fs; - let Inst{15-13} = 0x0; // cc + let Inst{15-13} = fcc; let Inst{12} = 0; let Inst{11-10} = fmt; let Inst{9-6} = cond; let Inst{5-0} = 0x3c; } +class C_COND_FM_MM fmt, bits<4> c> : CEQS_FM_MM { + let cond = c; +} + class BC1F_FM_MM tf> : MMArch { bits<16> offset; Modified: vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -1037,6 +1037,22 @@ void MipsAsmPrinter::PrintDebugValueComm // TODO: implement } +// Emit .dtprelword or .dtpreldword directive +// and value for debug thread local expression. +void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, + unsigned Size) const { + switch (Size) { + case 4: + OutStreamer->EmitDTPRel32Value(Value); + break; + case 8: + OutStreamer->EmitDTPRel64Value(Value); + break; + default: + llvm_unreachable("Unexpected size of expression value."); + } +} + // Align all targets of indirect branches on bundle size. Used only if target // is NaCl. void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) { Modified: vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.h ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.h Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.h Wed Feb 1 21:34:47 2017 (r313056) @@ -140,6 +140,7 @@ public: void EmitStartOfAsmFile(Module &M) override; void EmitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); + void EmitDebugValue(const MCExpr *Value, unsigned Size) const override; }; } Modified: vendor/llvm/dist/lib/Target/Mips/MipsFastISel.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsFastISel.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsFastISel.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -698,8 +698,8 @@ bool MipsFastISel::emitCmp(unsigned Resu unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); - emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( - Mips::FCC0, RegState::ImplicitDefine); + emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) + .addReg(RightReg); emitInst(CondMovOpc, ResultReg) .addReg(RegWithOne) .addReg(Mips::FCC0) Modified: vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td Wed Feb 1 21:34:47 2017 (r313056) @@ -219,6 +219,7 @@ class BC1F_FT, HARDFLOAT { let Defs = [FCC0]; let isCodeGenOnly = 1; + let hasFCCRegOperand = 1; } + +// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather +// duplicating the instruction definition for MIPS1 - MIPS3, we expand +// c.cond.ft if necessary, and reject it after constructing the +// instruction if the ISA doesn't support it. class C_COND_FT : - InstSE<(outs), (ins RC:$fs, RC:$ft), - !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, - FrmFR>, HARDFLOAT; + InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), + !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, + FrmFR>, HARDFLOAT { + let isCompare = 1; + let hasFCCRegOperand = 1; +} + multiclass C_COND_M fmt, InstrItinClass itin> { - def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM; - def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM; - def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM; - def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM; - def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM; - def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM; - def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM; - def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM; - def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM; - def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM; - def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM; - def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM; - def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM; - def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM; - def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM; - def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM; + def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.f."#NAME; + let isCommutable = 1; + } + def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.un."#NAME; + let isCommutable = 1; + } + def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.eq."#NAME; + let isCommutable = 1; + } + def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ueq."#NAME; + let isCommutable = 1; + } + def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.olt."#NAME; + } + def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ult."#NAME; + } + def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ole."#NAME; + } + def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ule."#NAME; + } + def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.sf."#NAME; + let isCommutable = 1; + } + def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ngle."#NAME; + } + def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.seq."#NAME; + let isCommutable = 1; + } + def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ngl."#NAME; + } + def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.lt."#NAME; + } + def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.nge."#NAME; + } + def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.le."#NAME; + } + def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM { + let BaseOpcode = "c.ngt."#NAME; + } } +let AdditionalPredicates = [NotInMicroMips] in { defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, FGR_32; let DecoderNamespace = "Mips64" in defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, FGR_64; - +} //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// @@ -549,13 +615,29 @@ def BC1TL : MMRel, BC1F_FT<"bc1tl", brta /// Floating Point Compare let AdditionalPredicates = [NotInMicroMips] in { def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, - ISA_MIPS1_NOT_32R6_64R6; + ISA_MIPS1_NOT_32R6_64R6 { + + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; + } def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_32; + ISA_MIPS1_NOT_32R6_64R6, FGR_32 { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; + } } let DecoderNamespace = "Mips64" in def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_64; + ISA_MIPS1_NOT_32R6_64R6, FGR_64 { + // FIXME: This is a required to work around the fact that thiese instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} //===----------------------------------------------------------------------===// // Floating Point Pseudo-Instructions @@ -602,15 +684,6 @@ def PseudoTRUNC_W_D : MipsAsmPseudoInst< //===----------------------------------------------------------------------===// // InstAliases. //===----------------------------------------------------------------------===// -def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, - ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, - ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, - ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, - ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; - def : MipsInstAlias <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, ISA_MIPS2, HARDFLOAT; @@ -630,6 +703,80 @@ def : MipsInstAlias def : MipsInstAlias <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, FGR_64, ISA_MIPS2, HARDFLOAT; + +multiclass C_COND_ALIASES { + def : MipsInstAlias("C_F_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_UN_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_EQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_UEQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_OLT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_ULT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_OLE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_ULE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_SF_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_NGLE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_SEQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_NGL_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_LT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_NGE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_LE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias("C_NGT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; +} + +multiclass BC1_ALIASES { + def : MipsInstAlias; + + def : MipsInstAlias; +} + +let AdditionalPredicates = [NotInMicroMips] in { + defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6; + defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm : BC1_ALIASES, ISA_MIPS1_NOT_32R6_64R6, + HARDFLOAT; + defm : BC1_ALIASES, ISA_MIPS2_NOT_32R6_64R6, + HARDFLOAT; +} //===----------------------------------------------------------------------===// // Floating Point Patterns //===----------------------------------------------------------------------===// Modified: vendor/llvm/dist/lib/Target/Mips/MipsInstrFormats.td ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsInstrFormats.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsInstrFormats.td Wed Feb 1 21:34:47 2017 (r313056) @@ -101,12 +101,15 @@ class MipsInst register and is + // present in MIPS-I to MIPS-III. - // TSFlags layout should be kept in sync with MipsInstrInfo.h. + // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h. let TSFlags{3-0} = FormBits; let TSFlags{4} = isCTI; let TSFlags{5} = hasForbiddenSlot; let TSFlags{6} = IsPCRelativeLoad; + let TSFlags{7} = hasFCCRegOperand; let DecoderNamespace = "Mips"; @@ -829,6 +832,7 @@ class BC1F_FM : StdArch class CEQS_FM fmt> : StdArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -837,7 +841,7 @@ class CEQS_FM fmt> : StdArch { let Inst{25-21} = fmt; let Inst{20-16} = ft; let Inst{15-11} = fs; - let Inst{10-8} = 0; // cc + let Inst{10-8} = fcc; let Inst{7-4} = 0x3; let Inst{3-0} = cond; } Modified: vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -148,3 +148,11 @@ MCSection *MipsTargetObjectFile::getSect // Otherwise, we work the same as ELF. return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Align); } + +const MCExpr * +MipsTargetObjectFile::getDebugThreadLocalSymbol(const MCSymbol *Sym) const { + const MCExpr *Expr = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + return MCBinaryExpr::createAdd( + Expr, MCConstantExpr::create(0x8000, getContext()), getContext()); +} Modified: vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.h ============================================================================== --- vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.h Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/Mips/MipsTargetObjectFile.h Wed Feb 1 21:34:47 2017 (r313056) @@ -42,6 +42,8 @@ class MipsTargetMachine; MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, unsigned &Align) const override; + /// Describe a TLS variable address within debug info. + const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; }; } // end namespace llvm Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.td ============================================================================== --- vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.td Wed Feb 1 21:34:47 2017 (r313056) @@ -1508,8 +1508,14 @@ def DCBTST : DCB_Form_hint<246, (outs), PPC970_DGroup_Single; } // hasSideEffects = 0 +def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), + "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; +def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), + "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; +def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), + "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def : Pat<(int_ppc_dcbt xoaddr:$dst), (DCBT 0, xoaddr:$dst)>; @@ -2381,6 +2387,13 @@ def MTSPR : XFXForm_1<31, 467, (outs), ( def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), "mftb $RT, $SPR", IIC_SprMFTB>; +def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), + "mfpmr $RT, $SPR", IIC_SprMFPMR>; + +def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), + "mtpmr $SPR, $RT", IIC_SprMTPMR>; + + // A pseudo-instruction used to implement the read of the 64-bit cycle counter // on a 32-bit target. let hasSideEffects = 1, usesCustomInserter = 1 in Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCSchedule.td ============================================================================== --- vendor/llvm/dist/lib/Target/PowerPC/PPCSchedule.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/PowerPC/PPCSchedule.td Wed Feb 1 21:34:47 2017 (r313056) @@ -118,6 +118,8 @@ def IIC_SprTLBIE : InstrItinClass; def IIC_SprABORT : InstrItinClass; def IIC_SprMSGSYNC : InstrItinClass; def IIC_SprSTOP : InstrItinClass; +def IIC_SprMFPMR : InstrItinClass; +def IIC_SprMTPMR : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE500mc.td ============================================================================== --- vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE500mc.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE500mc.td Wed Feb 1 21:34:47 2017 (r313056) @@ -249,6 +249,10 @@ def PPCE500mcItineraries : ProcessorItin InstrStage<5, [E500_SFX0]>], [8, 1], [E500_GPR_Bypass, E500_CR_Bypass]>, + InstrItinData, + InstrStage<4, [E500_SFX0]>], + [7, 1], // Latency = 4, Repeat rate = 4 + [E500_GPR_Bypass, E500_GPR_Bypass]>, InstrItinData, InstrStage<4, [E500_SFX0]>], [7, 1], // Latency = 4, Repeat rate = 4 @@ -257,6 +261,10 @@ def PPCE500mcItineraries : ProcessorItin InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1], // Latency = 1, Repeat rate = 1 [E500_GPR_Bypass, E500_CR_Bypass]>, + InstrItinData, + InstrStage<1, [E500_SFX0]>], + [4, 1], // Latency = 1, Repeat rate = 1 + [E500_CR_Bypass, E500_GPR_Bypass]>, InstrItinData, InstrStage<4, [E500_SFX0]>], [7, 1], // Latency = 4, Repeat rate = 4 Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE5500.td ============================================================================== --- vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE5500.td Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleE5500.td Wed Feb 1 21:34:47 2017 (r313056) @@ -313,20 +313,24 @@ def PPCE5500Itineraries : ProcessorItine InstrStage<5, [E5500_CFX_0]>], [9, 2], // Latency = 5, Repeat rate = 5 [E5500_GPR_Bypass, E5500_CR_Bypass]>, - InstrItinData, - InstrStage<4, [E5500_SFX0]>], + InstrItinData, + InstrStage<4, [E5500_CFX_0]>], [8, 2], // Latency = 4, Repeat rate = 4 [E5500_GPR_Bypass, E5500_GPR_Bypass]>, InstrItinData, InstrStage<1, [E5500_CFX_0]>], [5], // Latency = 1, Repeat rate = 1 [E5500_GPR_Bypass]>, + InstrItinData, + InstrStage<1, [E5500_CFX_0]>], + [5], // Latency = 1, Repeat rate = 1 + [E5500_GPR_Bypass]>, InstrItinData, InstrStage<4, [E5500_CFX_0]>], [8, 2], // Latency = 4, Repeat rate = 4 [NoBypass, E5500_GPR_Bypass]>, InstrItinData, - InstrStage<1, [E5500_SFX0, E5500_SFX1]>], + InstrStage<1, [E5500_CFX_0]>], [5], // Latency = 1, Repeat rate = 1 [E5500_GPR_Bypass]>, InstrItinData, Modified: vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -884,6 +884,10 @@ static Instruction *transformToIndexedCo if (!GEPLHS->hasAllConstantIndices()) return nullptr; + // Make sure the pointers have the same type. + if (GEPLHS->getType() != RHS->getType()) + return nullptr; + Value *PtrBase, *Index; std::tie(PtrBase, Index) = getAsConstantIndexedAddress(GEPLHS, DL); Modified: vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -502,7 +502,8 @@ static Instruction *combineLoadToOperati !DL.isNonIntegralPointerType(Ty)) { if (all_of(LI.users(), [&LI](User *U) { auto *SI = dyn_cast(U); - return SI && SI->getPointerOperand() != &LI; + return SI && SI->getPointerOperand() != &LI && + !SI->getPointerOperand()->isSwiftError(); })) { LoadInst *NewLoad = combineLoadToNewType( IC, LI, Modified: vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp Wed Feb 1 21:34:47 2017 (r313056) @@ -1705,7 +1705,10 @@ static bool runIPSCCP(Module &M, const D // If this is an exact definition of this function, then we can propagate // information about its result into callsites of it. - if (F.hasExactDefinition()) + // Don't touch naked functions. They may contain asm returning a + // value we don't see, so we may end up interprocedurally propagating + // the return value incorrectly. + if (F.hasExactDefinition() && !F.hasFnAttribute(Attribute::Naked)) Solver.AddTrackedFunction(&F); // If this function only has direct calls that we can see, we can track its Added: vendor/llvm/dist/test/CodeGen/SystemZ/pr31710.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/CodeGen/SystemZ/pr31710.ll Wed Feb 1 21:34:47 2017 (r313056) @@ -0,0 +1,39 @@ +; RUN: llc < %s -mtriple=s390x-redhat-linux | FileCheck %s +; +; Triggers a path in SelectionDAG's UpdateChains where a node is +; deleted but we try to read it later (pr31710), invoking UB in +; release mode or hitting an assert if they're enabled. + +; CHECK: btldata: +define void @btldata(i64* %u0, i32** %p0, i32** %p1, i32** %p3, i32** %p5, i32** %p7) { +entry: + %x0 = load i32*, i32** %p0, align 8, !tbaa !0 + store i64 0, i64* %u0, align 8, !tbaa !4 + %x1 = load i32*, i32** %p1, align 8, !tbaa !0 + %x2 = load i32, i32* %x1, align 4, !tbaa !6 + %x2ext = sext i32 %x2 to i64 + store i32 %x2, i32* %x1, align 4, !tbaa !6 + %x3 = load i32*, i32** %p3, align 8, !tbaa !0 + %ptr = getelementptr inbounds i32, i32* %x3, i64 %x2ext + %x4 = load i32, i32* %ptr, align 4, !tbaa !6 + %x4inc = add nsw i32 %x4, 1 + store i32 %x4inc, i32* %ptr, align 4, !tbaa !6 + store i64 undef, i64* %u0, align 8, !tbaa !4 + %x5 = load i32*, i32** %p5, align 8, !tbaa !0 + %x6 = load i32, i32* %x5, align 4, !tbaa !6 + store i32 %x6, i32* %x5, align 4, !tbaa !6 + %x7 = load i32*, i32** %p7, align 8, !tbaa !0 + %x8 = load i32, i32* %x7, align 4, !tbaa !6 + %x8inc = add nsw i32 %x8, 1 + store i32 %x8inc, i32* %x7, align 4, !tbaa !6 + ret void +} + +!0 = !{!1, !1, i64 0} +!1 = !{!"any pointer", !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} +!4 = !{!5, !5, i64 0} +!5 = !{!"long", !2, i64 0} +!6 = !{!7, !7, i64 0} +!7 = !{!"int", !2, i64 0} Added: vendor/llvm/dist/test/DebugInfo/Mips/tls.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/DebugInfo/Mips/tls.ll Wed Feb 1 21:34:47 2017 (r313056) @@ -0,0 +1,22 @@ +; RUN: llc -O0 -march=mips -mcpu=mips32r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-WORD +; RUN: llc -O0 -march=mips64 -mcpu=mips64r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-DWORD + +@x = thread_local global i32 5, align 4, !dbg !0 + +; CHECK-WORD: .dtprelword x+32768 +; CHECK-DWORD: .dtpreldword x+32768 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = !DIGlobalVariableExpression(var: !1) +!1 = distinct !DIGlobalVariable(name: "x", scope: !2, file: !3, line: 1, type: !6, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 4.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5) +!3 = !DIFile(filename: "tls.c", directory: "/tmp") +!4 = !{} +!5 = !{!0} +!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!7 = !{i32 2, !"Dwarf Version", i32 4} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{!"clang version 4.0.0"} Modified: vendor/llvm/dist/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt ============================================================================== --- vendor/llvm/dist/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt Wed Feb 1 21:34:47 2017 (r313056) @@ -134,3 +134,12 @@ 0x7c 0x0b 0x66 0x24 # CHECK: tlbsx 11, 12 0x7c 0x0b 0x67 0x24 + +# CHECK: mfpmr 5, 400 +0x7c 0xb0 0x62 0x9c +# CHECK: mtpmr 400, 6 +0x7c 0xd0 0x63 0x9c +# CHECK: icblc 0, 0, 8 +0x7c 0x00 0x41 0xcc +# CHECK: icbtls 0, 0, 9 +0x7c 0x00 0x4b 0xcc Added: vendor/llvm/dist/test/MC/MachO/ARM/no-tls-assert.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist/test/MC/MachO/ARM/no-tls-assert.ll Wed Feb 1 21:34:47 2017 (r313056) @@ -0,0 +1,28 @@ +; RUN: llc -filetype=obj -o - %s | llvm-objdump -section-headers - | FileCheck %s +; This should not trigger the "Creating regular section after DWARF" assert. +; CHECK: __text +; CHECK: __thread_ptr 00000004 +target triple = "thumbv7-apple-ios9.0.0" + +@b = external thread_local global i32 +define i32* @func(i32 %a) !dbg !9 { + ret i32* @b +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5, !6, !7} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "r.ii", directory: "/") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{i32 1, !"min_enum_size", i32 4} +!7 = !{i32 1, !"PIC Level", i32 2} +!9 = distinct !DISubprogram(name: "func", scope: !1, file: !1, line: 4, type: !10, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!10 = !DISubroutineType(types: !11) +!11 = !{null, !12} +!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!13 = !DILocalVariable(name: "a", arg: 1, scope: !9, file: !1, line: 4, type: !12) +!14 = !DIExpression() Modified: vendor/llvm/dist/test/MC/Mips/micromips/valid.s ============================================================================== --- vendor/llvm/dist/test/MC/Mips/micromips/valid.s Wed Feb 1 21:21:01 2017 (r313055) +++ vendor/llvm/dist/test/MC/Mips/micromips/valid.s Wed Feb 1 21:34:47 2017 (r313056) @@ -210,6 +210,42 @@ recip.s $f2, $f4 # CHECK: rec recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b] rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] +c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x55,0xce,0x24,0xbc] +c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x56,0x38,0xa0,0xbc] +c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x56,0x8a,0x84,0x3c] +c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x54,0xfe,0x80,0x3c] +c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x54,0x12,0x87,0xbc] +c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x54,0x98,0xc3,0xbc] *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***