Date: Thu, 5 Mar 2009 10:47:19 +0100 From: "Tassilo Philipp" <tphilipp@potion-studios.com> To: FreeBSD-gnats-submit@FreeBSD.org Subject: ports/132329: New port: devel/psptoolchain-binutils Message-ID: <20090305100349.017CA8FC18@mx1.freebsd.org> Resent-Message-ID: <200903051010.n25AA5NJ077621@freefall.freebsd.org>
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>Number: 132329 >Category: ports >Synopsis: New port: devel/psptoolchain-binutils >Confidential: no >Severity: non-critical >Priority: low >Responsible: freebsd-ports-bugs >State: open >Quarter: >Keywords: >Date-Required: >Class: change-request >Submitter-Id: current-users >Arrival-Date: Thu Mar 05 10:10:05 UTC 2009 >Closed-Date: >Last-Modified: >Originator: Tassilo Philipp >Release: FreeBSD 7.0-RELEASE amd64 >Organization: >Environment: System: FreeBSD amphore.potion-studios.com 7.0-RELEASE FreeBSD 7.0-RELEASE #0: Wed Aug 20 20:52:41 CEST 2008 tphilipp@amphore.potion-studios.com:/usr/obj/usr/src/sys/GENERIC amd64 >Description: >How-To-Repeat: >Fix: --- psptoolchain-binutils.shar begins here --- # This is a shell archive. Save it in a file, remove anything before # this line, and then unpack it by entering "sh file". Note, it may # create directories; files and directories will be owned by you and # have default permissions. # # This archive contains: # # psptoolchain-binutils # psptoolchain-binutils/distinfo # psptoolchain-binutils/Makefile # psptoolchain-binutils/pkg-descr # psptoolchain-binutils/files # psptoolchain-binutils/files/patch-bfd-cpu-mips.c # psptoolchain-binutils/files/patch-bfd-Makefile.am # psptoolchain-binutils/files/patch-bfd-version.h # psptoolchain-binutils/files/patch-config.sub # psptoolchain-binutils/files/patch-configure # psptoolchain-binutils/files/patch-gas-configure # psptoolchain-binutils/files/patch-include-bin-bugs.h # psptoolchain-binutils/files/patch-include-elf-mips.h # psptoolchain-binutils/files/patch-include-opcode-vfpu.h # psptoolchain-binutils/files/patch-ld-Makefile.am # psptoolchain-binutils/files/patch-ld-Makefile.in # psptoolchain-binutils/files/patch-opcodes-mips-dis.c # psptoolchain-binutils/files/patch-bfd-configure # psptoolchain-binutils/files/patch-bfd-archures.c # psptoolchain-binutils/files/patch-bfd-bfd-in2.h # psptoolchain-binutils/files/patch-bfd-elfxx-mips.c # psptoolchain-binutils/files/patch-bfd-Makefile.in # psptoolchain-binutils/files/patch-binutils-readelf.c # psptoolchain-binutils/files/patch-gas-config-tc-mips.c # psptoolchain-binutils/files/patch-gas-configure.in # psptoolchain-binutils/files/patch-gas-testsuite-gas-mips-mips.exp # psptoolchain-binutils/files/patch-include-elf-common.h # psptoolchain-binutils/files/patch-include-opcode-mips.h # psptoolchain-binutils/files/patch-ld-configure.tgt # psptoolchain-binutils/files/patch-ld-emulparams-elf_mipsallegrexel_psp.sh # psptoolchain-binutils/files/patch-ld-scripttempl-elf_psp.sc # psptoolchain-binutils/files/patch-opcodes-mips-opc.c # psptoolchain-binutils/files/patch-opcodes-configure # psptoolchain-binutils/pkg-plist # echo c - psptoolchain-binutils mkdir -p psptoolchain-binutils > /dev/null 2>&1 echo x - psptoolchain-binutils/distinfo sed 's/^X//' >psptoolchain-binutils/distinfo << 'END-of-psptoolchain-binutils/distinfo' XMD5 (binutils-2.16.1.tar.bz2) = 6a9d529efb285071dad10e1f3d2b2967 XSHA256 (binutils-2.16.1.tar.bz2) = 351a6846ee179a37ed87a487971547159a7f4f92a1dec598c727f184a0de61ae XSIZE (binutils-2.16.1.tar.bz2) = 12549917 END-of-psptoolchain-binutils/distinfo echo x - psptoolchain-binutils/Makefile sed 's/^X//' >psptoolchain-binutils/Makefile << 'END-of-psptoolchain-binutils/Makefile' X# New ports collection makefile for: psptoolchain-binutils X# Date created: 13 February 2009 X# Whom: Tassilo Philipp <tphilipp@potion-studios.com> X# X# $FreeBSD$ X# X XPORTNAME= binutils XPORTVERSION= 2.16.1 XCATEGORIES= devel XMASTER_SITES= ftp://ftp.gnu.org/pub/gnu/${PORTNAME}/ \ X ${MASTER_SITE_SOURCEWARE} XMASTER_SITE_SUBDIR= ${PORTNAME}/releases XPKGNAMEPREFIX= psptoolchain- X XMAINTAINER= tphilipp@potion-studios.com XCOMMENT= PlayStation Portable development toolchain ${PORTNAME} X XUSE_BZIP2= yes XUSE_GMAKE= yes X XHAS_CONFIGURE= yes XCONFIGURE_ARGS= --prefix=${PREFIX} --target="psp" --enable-install-libbfd --disable-nls X XMAN1= psp-addr2line.1 \ X psp-ar.1 \ X psp-as.1 \ X psp-c++filt.1 \ X psp-dlltool.1 \ X psp-gprof.1 \ X psp-ld.1 \ X psp-nlmconv.1 \ X psp-nm.1 \ X psp-objcopy.1 \ X psp-objdump.1 \ X psp-ranlib.1 \ X psp-readelf.1 \ X psp-size.1 \ X psp-strings.1 \ X psp-strip.1 \ X psp-windres.1 XINFO= as \ X bfd \ X binutils \ X configure \ X gprof \ X ld \ X standards X X.include <bsd.port.mk> END-of-psptoolchain-binutils/Makefile echo x - psptoolchain-binutils/pkg-descr sed 's/^X//' >psptoolchain-binutils/pkg-descr << 'END-of-psptoolchain-binutils/pkg-descr' XThe PlayStation Portable Toolchain is a collection of tools and utilities Xfor homebrew PSP development. X XWWW: http://www.ps2dev.org END-of-psptoolchain-binutils/pkg-descr echo c - psptoolchain-binutils/files mkdir -p psptoolchain-binutils/files > /dev/null 2>&1 echo x - psptoolchain-binutils/files/patch-bfd-cpu-mips.c sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-cpu-mips.c << 'END-of-psptoolchain-binutils/files/patch-bfd-cpu-mips.c' X--- bfd/cpu-mips.c.orig 2005-03-03 11:40:58.000000000 +0000 X+++ bfd/cpu-mips.c 2006-05-09 02:55:36.000000000 +0100 X@@ -86,6 +86,7 @@ X I_mipsisa64, X I_mipsisa64r2, X I_sb1, X+ I_allegrex, X }; X X #define NN(index) (&arch_info_struct[(index) + 1]) X@@ -118,7 +119,8 @@ X N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), X N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), X N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), X- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0), X+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)), X+ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0), X }; X X /* The default architecture is mips:3000, but with a machine number of END-of-psptoolchain-binutils/files/patch-bfd-cpu-mips.c echo x - psptoolchain-binutils/files/patch-bfd-Makefile.am sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-Makefile.am << 'END-of-psptoolchain-binutils/files/patch-bfd-Makefile.am' X--- bfd/Makefile.am.orig 2005-06-12 19:58:52.000000000 +0100 X+++ bfd/Makefile.am 2006-05-09 02:55:36.000000000 +0100 X@@ -3,7 +3,7 @@ X AUTOMAKE_OPTIONS = 1.9 cygnus X X # Uncomment the following line when doing a release. X-RELEASE=y X+#RELEASE=y X X INCDIR = $(srcdir)/../include X CSEARCH = -I. -I$(srcdir) -I$(INCDIR) END-of-psptoolchain-binutils/files/patch-bfd-Makefile.am echo x - psptoolchain-binutils/files/patch-bfd-version.h sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-version.h << 'END-of-psptoolchain-binutils/files/patch-bfd-version.h' X--- bfd/version.h.orig 2005-06-12 18:37:59.000000000 +0100 X+++ bfd/version.h 2006-05-09 02:55:36.000000000 +0100 X@@ -1,3 +1,3 @@ X-#define BFD_VERSION_DATE 20050612 X+#define BFD_VERSION_DATE (PSPDEV 20060116) X #define BFD_VERSION @bfd_version@ X #define BFD_VERSION_STRING @bfd_version_string@ END-of-psptoolchain-binutils/files/patch-bfd-version.h echo x - psptoolchain-binutils/files/patch-config.sub sed 's/^X//' >psptoolchain-binutils/files/patch-config.sub << 'END-of-psptoolchain-binutils/files/patch-config.sub' X--- config.sub.orig 2005-01-19 00:34:56.000000000 +0000 X+++ config.sub 2006-05-09 02:55:36.000000000 +0100 X@@ -253,6 +253,7 @@ X | mipsisa64sb1 | mipsisa64sb1el \ X | mipsisa64sr71k | mipsisa64sr71kel \ X | mipstx39 | mipstx39el \ X+ | mipsallegrex | mipsallegrexel \ X | mn10200 | mn10300 \ X | msp430 \ X | ns16k | ns32k \ X@@ -326,6 +327,7 @@ X | mipsisa64sb1-* | mipsisa64sb1el-* \ X | mipsisa64sr71k-* | mipsisa64sr71kel-* \ X | mipstx39-* | mipstx39el-* \ X+ | mipsallegrex-* | mipsallegrexel-* \ X | mmix-* \ X | msp430-* \ X | none-* | np1-* | ns16k-* | ns32k-* \ X@@ -665,6 +667,10 @@ X basic_machine=m68k-atari X os=-mint X ;; X+ psp) X+ basic_machine=mipsallegrexel-psp X+ os=-elf X+ ;; X mips3*-*) X basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` X ;; END-of-psptoolchain-binutils/files/patch-config.sub echo x - psptoolchain-binutils/files/patch-configure sed 's/^X//' >psptoolchain-binutils/files/patch-configure << 'END-of-psptoolchain-binutils/files/patch-configure' X--- configure.orig 2005-02-28 14:06:59.000000000 +0000 X+++ configure 2006-05-09 02:55:10.000000000 +0100 X@@ -1034,7 +1034,7 @@ X X # Some tools are only suitable for building in a "native" situation. X # Remove these if host!=target. X-native_only="autoconf automake libtool fileutils find gawk gettext gzip hello indent m4 rcs recode sed shellutils tar textutils uudecode wdiff gprof target-groff guile perl time ash bash bzip2 prms gnuserv target-gperf" X+native_only="autoconf automake libtool fileutils find gawk gettext gzip hello indent m4 rcs recode sed shellutils tar textutils uudecode wdiff target-groff guile perl time ash bash bzip2 prms gnuserv target-gperf" X X # Similarly, some are only suitable for cross toolchains. X # Remove these if host=target. X@@ -1516,7 +1516,7 @@ X noconfigdirs="$noconfigdirs target-newlib target-libgloss" X ;; X mips*-*-*) X- noconfigdirs="$noconfigdirs gprof ${libgcj}" X+ noconfigdirs="$noconfigdirs ${libgcj}" X ;; X romp-*-*) X noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes target-libgloss ${libgcj}" END-of-psptoolchain-binutils/files/patch-configure echo x - psptoolchain-binutils/files/patch-gas-configure sed 's/^X//' >psptoolchain-binutils/files/patch-gas-configure << 'END-of-psptoolchain-binutils/files/patch-gas-configure' X--- gas/configure.orig 2005-03-01 00:43:51.000000000 +0000 X+++ gas/configure 2006-05-09 02:55:36.000000000 +0100 X@@ -4537,6 +4537,9 @@ X mips64vr | mips64vrel) X mips_cpu=vr4100 X ;; X+ mipsallegrex | mipsallegrexel) X+ mips_cpu=allegrex X+ ;; X mipsisa32r2* | mipsisa64r2*) X mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` X ;; END-of-psptoolchain-binutils/files/patch-gas-configure echo x - psptoolchain-binutils/files/patch-include-bin-bugs.h sed 's/^X//' >psptoolchain-binutils/files/patch-include-bin-bugs.h << 'END-of-psptoolchain-binutils/files/patch-include-bin-bugs.h' X--- include/bin-bugs.h.orig 2004-07-23 16:40:19.000000000 +0100 X+++ include/bin-bugs.h 2006-05-09 02:55:36.000000000 +0100 X@@ -1,3 +1,3 @@ X #ifndef REPORT_BUGS_TO X-#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>" X+#define REPORT_BUGS_TO "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>" X #endif END-of-psptoolchain-binutils/files/patch-include-bin-bugs.h echo x - psptoolchain-binutils/files/patch-include-elf-mips.h sed 's/^X//' >psptoolchain-binutils/files/patch-include-elf-mips.h << 'END-of-psptoolchain-binutils/files/patch-include-elf-mips.h' X--- include/elf/mips.h.orig 2005-03-03 11:58:06.000000000 +0000 X+++ include/elf/mips.h 2006-05-09 02:55:36.000000000 +0100 X@@ -212,6 +212,7 @@ X #define E_MIPS_MACH_5400 0x00910000 X #define E_MIPS_MACH_5500 0x00980000 X #define E_MIPS_MACH_9000 0x00990000 X+#define E_MIPS_MACH_ALLEGREX 0x00A20000 X X /* Processor specific section indices. These sections do not actually X exist. Symbols with a st_shndx field corresponding to one of these END-of-psptoolchain-binutils/files/patch-include-elf-mips.h echo x - psptoolchain-binutils/files/patch-include-opcode-vfpu.h sed 's/^X//' >psptoolchain-binutils/files/patch-include-opcode-vfpu.h << 'END-of-psptoolchain-binutils/files/patch-include-opcode-vfpu.h' X--- include/opcode/vfpu.h.orig 1970-01-01 01:00:00.000000000 +0100 X+++ include/opcode/vfpu.h 2006-05-09 02:55:36.000000000 +0100 X@@ -0,0 +1,261 @@ X+#ifndef _VFPU_H_ X+#define _VFPU_H_ X+ X+//////////////////////////////////// X+// data type X+#define VFPU_MASK_DTYPE 0x8080 X+#define VFPU_QUAD 0x8080 X+#define VFPU_TRIPLE 0x8000 X+#define VFPU_PAIR 0x0080 X+#define VFPU_SINGLE 0x0000 X+ X+//////////////////////////////////// X+// register index X+#define VFPU_MASK_VT 0x7f0000 X+#define VFPU_MASK_VS 0x007f00 X+#define VFPU_MASK_VD 0x00007f X+ X+//////////////////////////////////// X+// condition and comapre inst X+#define VFPU_PADD_BIN_CMP 0x70 X+ X+//////////////////////////////////// X+// load/store left/right X+#define VFPU_MASK_LDST_LR 0x2 X+#define VFPU_LDST_L 0x0 X+#define VFPU_LDST_R 0x2 X+ X+//////////////////////////////////// X+// load/store memory/buffer X+#define VFPU_MASK_LDST_MB 0x2 X+#define VFPU_LDST_M 0x0 X+#define VFPU_LDST_B 0x2 X+ X+//////////////////////////////////// X+// coprocessor move X+#define VFPU_MASK_COP_MV 0xff80 X+#define VFPU_MASK_COP_MVC 0xff00 X+ X+//////////////////////////////////// X+// sync code X+#define VFPU_MASK_SYNC_CODE 0xffff X+#define VFPU_SYNC_CODE_DEFAULT 0x0320 X+#define VFPU_SYNC_CODE_NOP 0x0000 X+#define VFPU_SYNC_CODE_FLUSH 0x040d X+ X+//////////////////////////////////// X+#define VFPU_INST_BR_F 0x49000000 X+#define VFPU_MASK_BR_F 0xffe30000 X+#define VFPU_INST_BR_FL 0x49020000 X+#define VFPU_MASK_BR_FL 0xffe30000 X+#define VFPU_INST_BR_T 0x49010000 X+#define VFPU_MASK_BR_T 0xffe30000 X+#define VFPU_INST_BR_TL 0x49030000 X+#define VFPU_MASK_BR_TL 0xffe30000 X+ X+#define VFPU_INST_COP_LD_S 0xc8000000 X+#define VFPU_MASK_COP_LD_S 0xfc000000 X+#define VFPU_INST_COP_ST_S 0xe8000000 X+#define VFPU_MASK_COP_ST_S 0xfc000000 X+#define VFPU_INST_COP_LD_Q 0xd8000000 X+#define VFPU_MASK_COP_LD_Q 0xfc000000 X+#define VFPU_INST_COP_ST_Q 0xf8000000 X+#define VFPU_MASK_COP_ST_Q 0xfc000000 X+#define VFPU_INST_COP_LD_U 0xd4000000 X+#define VFPU_MASK_COP_LD_U 0xfc000000 X+#define VFPU_INST_COP_ST_U 0xf4000000 X+#define VFPU_MASK_COP_ST_U 0xfc000000 X+#define VFPU_INST_COP_MF 0x48600000 X+#define VFPU_MASK_COP_MF 0xffe00000 X+#define VFPU_INST_COP_MT 0x48e00000 X+#define VFPU_MASK_COP_MT 0xffe00000 X+ X+#define VFPU_INST_BIN_ADD 0x60000000 X+#define VFPU_MASK_BIN_ADD 0xff800000 X+#define VFPU_INST_BIN_SUB 0x60800000 X+#define VFPU_MASK_BIN_SUB 0xff800000 X+#define VFPU_INST_BIN_SBN 0x61000000 X+#define VFPU_MASK_BIN_SBN 0xff800000 X+#define VFPU_INST_BIN_DIV 0x63800000 X+#define VFPU_MASK_BIN_DIV 0xff800000 X+#define VFPU_INST_BIN_MUL 0x64000000 X+#define VFPU_MASK_BIN_MUL 0xff800000 X+#define VFPU_INST_BIN_DOT 0x64800000 X+#define VFPU_MASK_BIN_DOT 0xff800000 X+#define VFPU_INST_BIN_SCL 0x65000000 X+#define VFPU_MASK_BIN_SCL 0xff800000 X+#define VFPU_INST_BIN_HDP 0x66000000 X+#define VFPU_MASK_BIN_HDP 0xff800000 X+#define VFPU_INST_BIN_CRS 0x66800000 X+#define VFPU_MASK_BIN_CRS 0xff800000 X+#define VFPU_INST_BIN_DET 0x67000000 X+#define VFPU_MASK_BIN_DET 0xff800000 X+#define VFPU_INST_BIN_CMP 0x6c000000 X+#define VFPU_MASK_BIN_CMP 0xff800000 X+#define VFPU_INST_BIN_MIN 0x6d000000 X+#define VFPU_MASK_BIN_MIN 0xff800000 X+#define VFPU_INST_BIN_MAX 0x6d800000 X+#define VFPU_MASK_BIN_MAX 0xff800000 X+#define VFPU_INST_BIN_SCMP 0x6e800000 X+#define VFPU_MASK_BIN_SCMP 0xff800000 X+#define VFPU_INST_BIN_SGE 0x6f000000 X+#define VFPU_MASK_BIN_SGE 0xff800000 X+#define VFPU_INST_BIN_SLT 0x6f800000 X+#define VFPU_MASK_BIN_SLT 0xff800000 X+ X+#define VFPU_INST_UNR_MOV 0xd0000000 X+#define VFPU_MASK_UNR_MOV 0xffff0000 X+#define VFPU_INST_UNR_ABS 0xd0010000 X+#define VFPU_MASK_UNR_ABS 0xffff0000 X+#define VFPU_INST_UNR_NEG 0xd0020000 X+#define VFPU_MASK_UNR_NEG 0xffff0000 X+#define VFPU_INST_UNR_IDT 0xd0030000 X+#define VFPU_MASK_UNR_IDT 0xffff0000 X+#define VFPU_INST_UNR_SAT0 0xd0040000 X+#define VFPU_MASK_UNR_SAT0 0xffff0000 X+#define VFPU_INST_UNR_SAT1 0xd0050000 X+#define VFPU_MASK_UNR_SAT1 0xffff0000 X+#define VFPU_INST_UNR_ZERO 0xd0060000 X+#define VFPU_MASK_UNR_ZERO 0xffff0000 X+#define VFPU_INST_UNR_ONE 0xd0070000 X+#define VFPU_MASK_UNR_ONE 0xffff0000 X+#define VFPU_INST_UNR_RCP 0xd0100000 X+#define VFPU_MASK_UNR_RCP 0xffff0000 X+#define VFPU_INST_UNR_RSQ 0xd0110000 X+#define VFPU_MASK_UNR_RSQ 0xffff0000 X+#define VFPU_INST_UNR_SIN 0xd0120000 X+#define VFPU_MASK_UNR_SIN 0xffff0000 X+#define VFPU_INST_UNR_COS 0xd0130000 X+#define VFPU_MASK_UNR_COS 0xffff0000 X+#define VFPU_INST_UNR_EXP2 0xd0140000 X+#define VFPU_MASK_UNR_EXP2 0xffff0000 X+#define VFPU_INST_UNR_LOG2 0xd0150000 X+#define VFPU_MASK_UNR_LOG2 0xffff0000 X+#define VFPU_INST_UNR_SQR 0xd0160000 X+#define VFPU_MASK_UNR_SQR 0xffff0000 X+#define VFPU_INST_UNR_ASIN 0xd0170000 X+#define VFPU_MASK_UNR_ASIN 0xffff0000 X+#define VFPU_INST_UNR_NRCP 0xd0180000 X+#define VFPU_MASK_UNR_NRCP 0xffff0000 X+#define VFPU_INST_UNR_NSIN 0xd01a0000 X+#define VFPU_MASK_UNR_NSIN 0xffff0000 X+#define VFPU_INST_UNR_REXP2 0xd01c0000 X+#define VFPU_MASK_UNR_REXP2 0xffff0000 X+#define VFPU_INST_UNR_RNDS 0xd0200000 X+#define VFPU_MASK_UNR_RNDS 0xffff0000 X+#define VFPU_INST_UNR_RNDI 0xd0210000 X+#define VFPU_MASK_UNR_RNDI 0xffff0000 X+#define VFPU_INST_UNR_RNDF1 0xd0220000 X+#define VFPU_MASK_UNR_RNDF1 0xffff0000 X+#define VFPU_INST_UNR_RNDF2 0xd0230000 X+#define VFPU_MASK_UNR_RNDF2 0xffff0000 X+#define VFPU_INST_UNR_F2H 0xd0320000 X+#define VFPU_MASK_UNR_F2H 0xffff0000 X+#define VFPU_INST_UNR_H2F 0xd0330000 X+#define VFPU_MASK_UNR_H2F 0xffff0000 X+#define VFPU_INST_UNR_SBZ 0xd0360000 X+#define VFPU_MASK_UNR_SBZ 0xffff0000 X+#define VFPU_INST_UNR_LGB 0xd0370000 X+#define VFPU_MASK_UNR_LGB 0xffff0000 X+#define VFPU_INST_UNR_US2I 0xd03a0000 X+#define VFPU_MASK_UNR_US2I 0xffff0000 X+#define VFPU_INST_UNR_S2I 0xd03b0000 X+#define VFPU_MASK_UNR_S2I 0xffff0000 X+#define VFPU_INST_UNR_I2UC 0xd03c0000 X+#define VFPU_MASK_UNR_I2UC 0xffff0000 X+#define VFPU_INST_UNR_I2C 0xd03d0000 X+#define VFPU_MASK_UNR_I2C 0xffff0000 X+#define VFPU_INST_UNR_I2US 0xd03e0000 X+#define VFPU_MASK_UNR_I2US 0xffff0000 X+#define VFPU_INST_UNR_I2S 0xd03f0000 X+#define VFPU_MASK_UNR_I2S 0xffff0000 X+#define VFPU_INST_UNR_SRT1 0xd0400000 X+#define VFPU_MASK_UNR_SRT1 0xffff0000 X+#define VFPU_INST_UNR_SRT2 0xd0410000 X+#define VFPU_MASK_UNR_SRT2 0xffff0000 X+#define VFPU_INST_UNR_BFY1 0xd0420000 X+#define VFPU_MASK_UNR_BFY1 0xffff0000 X+#define VFPU_INST_UNR_BFY2 0xd0430000 X+#define VFPU_MASK_UNR_BFY2 0xffff0000 X+#define VFPU_INST_UNR_OCP 0xd0440000 X+#define VFPU_MASK_UNR_OCP 0xffff0000 X+#define VFPU_INST_UNR_SOCP 0xd0450000 X+#define VFPU_MASK_UNR_SOCP 0xffff0000 X+#define VFPU_INST_UNR_FAD 0xd0460000 X+#define VFPU_MASK_UNR_FAD 0xffff0000 X+#define VFPU_INST_UNR_AVG 0xd0470000 X+#define VFPU_MASK_UNR_AVG 0xffff0000 X+#define VFPU_INST_UNR_SRT3 0xd0480000 X+#define VFPU_MASK_UNR_SRT3 0xffff0000 X+#define VFPU_INST_UNR_SRT4 0xd0490000 X+#define VFPU_MASK_UNR_SRT4 0xffff0000 X+#define VFPU_INST_UNR_SGN 0xd04a0000 X+#define VFPU_MASK_UNR_SGN 0xffff0000 X+#define VFPU_INST_UNR_CF 0xd0500000 X+#define VFPU_MASK_UNR_CF 0xffff0080 X+#define VFPU_INST_UNR_CT 0xd0510000 X+#define VFPU_MASK_UNR_CT 0xffff8000 X+#define VFPU_INST_UNR_T4444 0xd0590000 X+#define VFPU_MASK_UNR_T4444 0xffff0000 X+#define VFPU_INST_UNR_T5551 0xd05a0000 X+#define VFPU_MASK_UNR_T5551 0xffff0000 X+#define VFPU_INST_UNR_T5650 0xd05b0000 X+#define VFPU_MASK_UNR_T5650 0xffff0000 X+#define VFPU_INST_UNR_CST 0xd0600000 X+#define VFPU_MASK_UNR_CST 0xffe00000 X+ X+#define VFPU_INST_UNRI_F2I_N 0xd2000000 X+#define VFPU_MASK_UNRI_F2I_N 0xffe00000 X+#define VFPU_INST_UNRI_F2I_Z 0xd2200000 X+#define VFPU_MASK_UNRI_F2I_Z 0xffe00000 X+#define VFPU_INST_UNRI_F2I_U 0xd2400000 X+#define VFPU_MASK_UNRI_F2I_U 0xffe00000 X+#define VFPU_INST_UNRI_F2I_D 0xd2600000 X+#define VFPU_MASK_UNRI_F2I_D 0xffe00000 X+#define VFPU_INST_UNRI_I2F 0xd2800000 X+#define VFPU_MASK_UNRI_I2F 0xffe00000 X+#define VFPU_INST_UNRI_CMOV_T 0xd2a00000 X+#define VFPU_MASK_UNRI_CMOV_T 0xfff80000 X+#define VFPU_INST_UNRI_CMOV_F 0xd2a80000 X+#define VFPU_MASK_UNRI_CMOV_F 0xfff80000 X+#define VFPU_INST_UNRI_WBN 0xd3000000 X+#define VFPU_MASK_UNRI_WBN 0xff000000 X+ X+#define VFPU_INST_PFX_RA 0xdc000000 X+#define VFPU_MASK_PFX_RA 0xff000000 X+#define VFPU_INST_PFX_RB 0xdd000000 X+#define VFPU_MASK_PFX_RB 0xff000000 X+#define VFPU_INST_PFX_W 0xde000000 X+#define VFPU_MASK_PFX_W 0xff000000 X+#define VFPU_INST_IIM 0xdf000000 X+#define VFPU_MASK_IIM 0xff800000 X+#define VFPU_INST_FIM 0xdf800000 X+#define VFPU_MASK_FIM 0xff800000 X+ X+#define VFPU_INST_RPT_MMUL 0xf0000000 X+#define VFPU_MASK_RPT_MMUL 0xff800000 X+#define VFPU_INST_RPT_TFM2 0xf0800000 X+#define VFPU_MASK_RPT_TFM2 0xff800000 X+#define VFPU_INST_RPT_TFM3 0xf1000000 X+#define VFPU_MASK_RPT_TFM3 0xff800000 X+#define VFPU_INST_RPT_TFM4 0xf1800000 X+#define VFPU_MASK_RPT_TFM4 0xff800000 X+#define VFPU_INST_RPT_MSCL 0xf2000000 X+#define VFPU_MASK_RPT_MSCL 0xff800000 X+#define VFPU_INST_RPT_QMUL 0xf2800000 X+#define VFPU_MASK_RPT_QMUL 0xff800000 X+#define VFPU_INST_RPT_MMOV 0xf3800000 X+#define VFPU_MASK_RPT_MMOV 0xffff0000 X+#define VFPU_INST_RPT_MIDT 0xf3830000 X+#define VFPU_MASK_RPT_MIDT 0xffff0000 X+#define VFPU_INST_RPT_MZERO 0xf3860000 X+#define VFPU_MASK_RPT_MZERO 0xffff0000 X+#define VFPU_INST_RPT_MONE 0xf3870000 X+#define VFPU_MASK_RPT_MONE 0xffff0000 X+#define VFPU_INST_RPT_ROT 0xf3a00000 X+#define VFPU_MASK_RPT_ROT 0xffe00000 X+ X+#define VFPU_INST_SYNC 0xffff0000 X+#define VFPU_MASK_SYNC 0xffff0000 X+ X+#endif /* _VFPU_H_ */ END-of-psptoolchain-binutils/files/patch-include-opcode-vfpu.h echo x - psptoolchain-binutils/files/patch-ld-Makefile.am sed 's/^X//' >psptoolchain-binutils/files/patch-ld-Makefile.am << 'END-of-psptoolchain-binutils/files/patch-ld-Makefile.am' X--- ld/Makefile.am.orig 2005-01-20 19:37:49.000000000 +0000 X+++ ld/Makefile.am 2006-05-09 02:55:36.000000000 +0100 X@@ -190,6 +190,7 @@ X eelf_i386_chaos.o \ X eelf_i386_fbsd.o \ X eelf_i386_ldso.o \ X+ eelf_mipsallegrexel_psp.o \ X eelf_s390.o \ X egld960.o \ X egld960coff.o \ X@@ -864,6 +865,9 @@ X eelf_i386_ldso.c: $(srcdir)/emulparams/elf_i386_ldso.sh \ X $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} X ${GENSCRIPTS} elf_i386_ldso "$(tdir_elf_i386_ldso)" X+eelf_mipsallegrexel_psp.c: $(srcdir)/emulparams/elf_mipsallegrexel_psp.sh \ X+ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf_psp.sc ${GEN_DEPENDS} X+ ${GENSCRIPTS} elf_mipsallegrexel_psp "$(tdir_elf_mipsallegrexel_psp)" X eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \ X $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} X ${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)" END-of-psptoolchain-binutils/files/patch-ld-Makefile.am echo x - psptoolchain-binutils/files/patch-ld-Makefile.in sed 's/^X//' >psptoolchain-binutils/files/patch-ld-Makefile.in << 'END-of-psptoolchain-binutils/files/patch-ld-Makefile.in' X--- ld/Makefile.in.orig 2005-01-23 05:36:37.000000000 +0000 X+++ ld/Makefile.in 2006-05-09 02:55:36.000000000 +0100 X@@ -315,6 +315,7 @@ X eelf_i386_chaos.o \ X eelf_i386_fbsd.o \ X eelf_i386_ldso.o \ X+ eelf_mipsallegrexel_psp.o \ X eelf_s390.o \ X egld960.o \ X egld960coff.o \ X@@ -1601,6 +1602,9 @@ X eelf_i386_ldso.c: $(srcdir)/emulparams/elf_i386_ldso.sh \ X $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} X ${GENSCRIPTS} elf_i386_ldso "$(tdir_elf_i386_ldso)" X+eelf_mipsallegrexel_psp.c: $(srcdir)/emulparams/elf_mipsallegrexel_psp.sh \ X+ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf_psp.sc ${GEN_DEPENDS} X+ ${GENSCRIPTS} elf_mipsallegrexel_psp "$(tdir_elf_mipsallegrexel_psp)" X eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \ X $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} X ${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)" END-of-psptoolchain-binutils/files/patch-ld-Makefile.in echo x - psptoolchain-binutils/files/patch-opcodes-mips-dis.c sed 's/^X//' >psptoolchain-binutils/files/patch-opcodes-mips-dis.c << 'END-of-psptoolchain-binutils/files/patch-opcodes-mips-dis.c' X--- opcodes/mips-dis.c.orig 2005-03-03 11:49:50.000000000 +0000 X+++ opcodes/mips-dis.c 2006-05-09 02:55:36.000000000 +0100 X@@ -140,6 +140,139 @@ X "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", X }; X X+static const char * const vfpu_sreg_names[128] = { X+ "S000", "S010", "S020", "S030", "S100", "S110", "S120", "S130", X+ "S200", "S210", "S220", "S230", "S300", "S310", "S320", "S330", X+ "S400", "S410", "S420", "S430", "S500", "S510", "S520", "S530", X+ "S600", "S610", "S620", "S630", "S700", "S710", "S720", "S730", X+ "S001", "S011", "S021", "S031", "S101", "S111", "S121", "S131", X+ "S201", "S211", "S221", "S231", "S301", "S311", "S321", "S331", X+ "S401", "S411", "S421", "S431", "S501", "S511", "S521", "S531", X+ "S601", "S611", "S621", "S631", "S701", "S711", "S721", "S731", X+ "S002", "S012", "S022", "S032", "S102", "S112", "S122", "S132", X+ "S202", "S212", "S222", "S232", "S302", "S312", "S322", "S332", X+ "S402", "S412", "S422", "S432", "S502", "S512", "S522", "S532", X+ "S602", "S612", "S622", "S632", "S702", "S712", "S722", "S732", X+ "S003", "S013", "S023", "S033", "S103", "S113", "S123", "S133", X+ "S203", "S213", "S223", "S233", "S303", "S313", "S323", "S333", X+ "S403", "S413", "S423", "S433", "S503", "S513", "S523", "S533", X+ "S603", "S613", "S623", "S633", "S703", "S713", "S723", "S733" X+}; X+ X+static const char * const vfpu_vpreg_names[128] = { X+ "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130", X+ "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330", X+ "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530", X+ "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730", X+ "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103", X+ "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303", X+ "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503", X+ "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703", X+ "C002", "C012", "C022", "C032", "C102", "C112", "C122", "C132", X+ "C202", "C212", "C222", "C232", "C302", "C312", "C322", "C332", X+ "C402", "C412", "C422", "C432", "C502", "C512", "C522", "C532", X+ "C602", "C612", "C622", "C632", "C702", "C712", "C722", "C732", X+ "R020", "R021", "R022", "R023", "R120", "R121", "R122", "R123", X+ "R220", "R221", "R222", "R223", "R320", "R321", "R322", "R323", X+ "R420", "R421", "R422", "R423", "R520", "R521", "R522", "R523", X+ "R620", "R621", "R622", "R623", "R720", "R721", "R722", "R723" X+}; X+ X+static const char * const vfpu_vtreg_names[128] = { X+ "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130", X+ "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330", X+ "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530", X+ "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730", X+ "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103", X+ "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303", X+ "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503", X+ "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703", X+ "C001", "C011", "C021", "C031", "C101", "C111", "C121", "C131", X+ "C201", "C211", "C221", "C231", "C301", "C311", "C321", "C331", X+ "C401", "C411", "C421", "C431", "C501", "C511", "C521", "C531", X+ "C601", "C611", "C621", "C631", "C701", "C711", "C721", "C731", X+ "R010", "R011", "R012", "R013", "R110", "R111", "R112", "R113", X+ "R210", "R211", "R212", "R213", "R310", "R311", "R312", "R313", X+ "R410", "R411", "R412", "R413", "R510", "R511", "R512", "R513", X+ "R610", "R611", "R612", "R613", "R710", "R711", "R712", "R713" X+}; X+ X+static const char * const vfpu_vqreg_names[128] = { X+ "C000", "C010", "C020", "C030", "C100", "C110", "C120", "C130", X+ "C200", "C210", "C220", "C230", "C300", "C310", "C320", "C330", X+ "C400", "C410", "C420", "C430", "C500", "C510", "C520", "C530", X+ "C600", "C610", "C620", "C630", "C700", "C710", "C720", "C730", X+ "R000", "R001", "R002", "R003", "R100", "R101", "R102", "R103", X+ "R200", "R201", "R202", "R203", "R300", "R301", "R302", "R303", X+ "R400", "R401", "R402", "R403", "R500", "R501", "R502", "R503", X+ "R600", "R601", "R602", "R603", "R700", "R701", "R702", "R703", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "" X+}; X+ X+static const char * const vfpu_mpreg_names[128] = { X+ "M000", "", "M020", "", "M100", "", "M120", "", X+ "M200", "", "M220", "", "M300", "", "M320", "", X+ "M400", "", "M420", "", "M500", "", "M520", "", X+ "M600", "", "M620", "", "M700", "", "M720", "", X+ "E000", "", "E002", "", "E100", "", "E102", "", X+ "E200", "", "E202", "", "E300", "", "E302", "", X+ "E400", "", "E402", "", "E500", "", "E502", "", X+ "E600", "", "E602", "", "E700", "", "E702", "", X+ "M002", "", "M022", "", "M102", "", "M122", "", X+ "M202", "", "M222", "", "M302", "", "M322", "", X+ "M402", "", "M422", "", "M502", "", "M522", "", X+ "M602", "", "M622", "", "M702", "", "M722", "", X+ "E020", "", "E022", "", "E120", "", "E122", "", X+ "E220", "", "E222", "", "E320", "", "E322", "", X+ "E420", "", "E422", "", "E520", "", "E522", "", X+ "E620", "", "E622", "", "E720", "", "E722", "" X+}; X+ X+static const char * const vfpu_mtreg_names[128] = { X+ "M000", "M010", "", "", "M100", "M110", "", "", X+ "M200", "M210", "", "", "M300", "M310", "", "", X+ "M400", "M410", "", "", "M500", "M510", "", "", X+ "M600", "M610", "", "", "M700", "M710", "", "", X+ "E000", "E001", "", "", "E100", "E101", "", "", X+ "E200", "E201", "", "", "E300", "E301", "", "", X+ "E400", "E401", "", "", "E500", "E501", "", "", X+ "E600", "E601", "", "", "E700", "E701", "", "", X+ "M001", "M011", "", "", "M101", "M111", "", "", X+ "M201", "M211", "", "", "M301", "M311", "", "", X+ "M401", "M411", "", "", "M501", "M511", "", "", X+ "M601", "M611", "", "", "M701", "M711", "", "", X+ "E010", "E011", "", "", "E110", "E111", "", "", X+ "E210", "E211", "", "", "E310", "E311", "", "", X+ "E410", "E411", "", "", "E510", "E511", "", "", X+ "E610", "E611", "", "", "E710", "E711", "", "" X+}; X+ X+static const char * const vfpu_mqreg_names[128] = { X+ "M000", "", "", "", "M100", "", "", "", X+ "M200", "", "", "", "M300", "", "", "", X+ "M400", "", "", "", "M500", "", "", "", X+ "M600", "", "", "", "M700", "", "", "", X+ "E000", "", "", "", "E100", "", "", "", X+ "E200", "", "", "", "E300", "", "", "", X+ "E400", "", "", "", "E500", "", "", "", X+ "E600", "", "", "", "E700", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "", X+ "", "", "", "", "", "", "", "" X+}; X+ X static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { X { 16, 1, "c0_config1" }, X { 16, 2, "c0_config2" }, X@@ -288,6 +421,54 @@ X "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" X }; X X+static const char * const vfpu_cond_names[16] = { X+ "FL", "EQ", "LT", "LE", "TR", "NE", "GE", "GT", X+ "EZ", "EN", "EI", "ES", "NZ", "NN", "NI", "NS" X+}; X+ X+static const char * const vfpu_const_names[20] = { X+ "", X+ "VFPU_HUGE", X+ "VFPU_SQRT2", X+ "VFPU_SQRT1_2", X+ "VFPU_2_SQRTPI", X+ "VFPU_2_PI", X+ "VFPU_1_PI", X+ "VFPU_PI_4", X+ "VFPU_PI_2", X+ "VFPU_PI", X+ "VFPU_E", X+ "VFPU_LOG2E", X+ "VFPU_LOG10E", X+ "VFPU_LN2", X+ "VFPU_LN10", X+ "VFPU_2PI", X+ "VFPU_PI_6", X+ "VFPU_LOG10TWO", X+ "VFPU_LOG2TEN", X+ "VFPU_SQRT3_2" X+}; X+ X+#define VFPU_NUM_CONSTANTS \ X+ ((sizeof vfpu_const_names) / (sizeof (vfpu_const_names[0]))) X+const unsigned int vfpu_num_constants = VFPU_NUM_CONSTANTS; X+ X+static const char * const vfpu_rwb_names[4] = { X+ "wt", "wb", "", "" X+}; X+ X+static const char * const pfx_cst_names[8] = { X+ "0", "1", "2", "1/2", "3", "1/3", "1/4", "1/6" X+}; X+ X+static const char * const pfx_swz_names[4] = { X+ "x", "y", "z", "w" X+}; X+ X+static const char * const pfx_sat_names[4] = { X+ "", "[0:1]", "", "[-1:1]" X+}; X+ X struct mips_abi_choice { X const char *name; X const char * const *gpr_names; X@@ -359,6 +540,8 @@ X mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, X { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, X mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, X+ { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2, X+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, X X /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. X Note that MIPS-3D and MDMX are not applicable to MIPS32. (See X@@ -1031,6 +1214,349 @@ X (l >> OP_SH_FT) & OP_MASK_FT); X break; X X+ case '?': X+ /* VFPU extensions. */ X+ d++; X+ switch (*d) X+ { X+ case '\0': X+ /* xgettext:c-format */ X+ (*info->fprintf_func) (info->stream, X+ _("# internal error, incomplete VFPU extension sequence (?)")); X+ return; X+ X+ case 'o': X+ delta = (l >> OP_SH_VFPU_DELTA) & OP_MASK_VFPU_DELTA; X+ if (delta & 0x8000) X+ delta |= ~0xffff; X+ (*info->fprintf_func) (info->stream, "%d", X+ delta); X+ break; X+ X+ case '0': X+ case '1': X+ case '2': X+ case '3': X+ { X+ unsigned int pos = *d, base = '0'; X+ unsigned int negation = (l >> (pos - (base - VFPU_SH_PFX_NEG))) & VFPU_MASK_PFX_NEG; X+ unsigned int constant = (l >> (pos - (base - VFPU_SH_PFX_CST))) & VFPU_MASK_PFX_CST; X+ unsigned int abs_consthi = X+ (l >> (pos - (base - VFPU_SH_PFX_ABS_CSTHI))) & VFPU_MASK_PFX_ABS_CSTHI; X+ unsigned int swz_constlo = (l >> ((pos - base) * 2)) & VFPU_MASK_PFX_SWZ_CSTLO; X+ X+ if (negation) X+ (*info->fprintf_func) (info->stream, "-"); X+ if (constant) X+ { X+ (*info->fprintf_func) (info->stream, "%s", X+ pfx_cst_names[(abs_consthi << 2) | swz_constlo]); X+ } X+ else X+ { X+ if (abs_consthi) X+ (*info->fprintf_func) (info->stream, "|%s|", X+ pfx_swz_names[swz_constlo]); X+ else X+ (*info->fprintf_func) (info->stream, "%s", X+ pfx_swz_names[swz_constlo]); X+ } X+ } X+ break; X+ X+ case '4': X+ case '5': X+ case '6': X+ case '7': X+ { X+ unsigned int pos = *d, base = '4'; X+ unsigned int mask = (l >> (pos - (base - VFPU_SH_PFX_MASK))) & VFPU_MASK_PFX_MASK; X+ unsigned int saturation = (l >> ((pos - base) * 2)) & VFPU_MASK_PFX_SAT; X+ X+ if (mask) X+ (*info->fprintf_func) (info->stream, "m"); X+ else X+ (*info->fprintf_func) (info->stream, "%s", X+ pfx_sat_names[saturation]); X+ } X+ break; X+ X+ case 'a': X+ { X+ unsigned int c = (l >> OP_SH_VFPU_CONST) & OP_MASK_VFPU_CONST; X+ if (c < vfpu_num_constants) X+ { X+ (*info->fprintf_func) (info->stream, "%s", X+ vfpu_const_names[c]); X+ } X+ break; X+ } X+ X+ case 'b': X+ /* 5-bit immediate value. */ X+ (*info->fprintf_func) (info->stream, "%d", X+ (l >> OP_SH_VFPU_IMM5) & OP_MASK_VFPU_IMM5); X+ break; X+ X+ case 'c': X+ /* VFPU condition code. */ X+ (*info->fprintf_func) (info->stream, "%d", X+ (l >> OP_SH_VFPU_CC) & OP_MASK_VFPU_CC); X+ break; X+ X+ case 'e': X+ /* 3-bit immediate value. */ X+ (*info->fprintf_func) (info->stream, "%d", X+ (l >> OP_SH_VFPU_IMM3) & OP_MASK_VFPU_IMM3); X+ break; X+ X+ case 'f': X+ /* Conditional compare. */ X+ (*info->fprintf_func) (info->stream, "%s", X+ vfpu_cond_names[(l >> OP_SH_VFPU_COND) & OP_MASK_VFPU_COND]); X+ /* Apparently this specifier is unused. */ X+ d++; X+ break; X+ X+ case 'i': X+ /* 8-bit immediate value. */ X+ (*info->fprintf_func) (info->stream, "0x%02x", X+ (l >> OP_SH_VFPU_IMM8) & OP_MASK_VFPU_IMM8); X+ break; X+ X+ case 'q': X+ /* VFPU control register (vmtvc). */ X+ (*info->fprintf_func) (info->stream, "$%d", X+ (l >> OP_SH_VFPU_VMTVC) & OP_MASK_VFPU_VMTVC); X+ break; X+ X+ case 'r': X+ /* VFPU control register (vmfvc). */ X+ (*info->fprintf_func) (info->stream, "$%d", X+ (l >> OP_SH_VFPU_VMFVC) & OP_MASK_VFPU_VMFVC); X+ break; X+ X+ case 'u': X+ /* Convert a VFPU 16-bit floating-point number to IEEE754. */ X+ { X+ union float2int { X+ unsigned int i; X+ float f; X+ } float2int; X+ unsigned short float16 = (l >> OP_SH_VFPU_FLOAT16) & OP_MASK_VFPU_FLOAT16; X+ unsigned int sign = (float16 >> VFPU_SH_FLOAT16_SIGN) & VFPU_MASK_FLOAT16_SIGN; X+ int exponent = (float16 >> VFPU_SH_FLOAT16_EXP) & VFPU_MASK_FLOAT16_EXP; X+ unsigned int fraction = float16 & VFPU_MASK_FLOAT16_FRAC; X+ char signchar = '+' + ((sign == 1) * 2); X+ X+ if (exponent == VFPU_FLOAT16_EXP_MAX) X+ { X+ if (fraction == 0) X+ (*info->fprintf_func) (info->stream, "%cInf", signchar); X+ else X+ (*info->fprintf_func) (info->stream, "%cNaN", signchar); X+ } X+ else if (exponent == 0 && fraction == 0) X+ { X+ (*info->fprintf_func) (info->stream, "%c0", signchar); X+ } X+ else X+ { X+ if (exponent == 0) X+ { X+ do X+ { X+ fraction <<= 1; X+ exponent--; X+ } X+ while (!(fraction & (VFPU_MASK_FLOAT16_FRAC + 1))); X+ X+ fraction &= VFPU_MASK_FLOAT16_FRAC; X+ } X+ X+ /* Convert to 32-bit single-precision IEEE754. */ X+ float2int.i = sign << 31; X+ float2int.i |= (exponent + 112) << 23; X+ float2int.i |= fraction << 13; X+ (*info->fprintf_func) (info->stream, "%g", float2int.f); X+ } X+ } X+ break; X+ X+ case 'w': X+ { X+ const char *elements[4]; X+ unsigned int opcode = l & VFPU_MASK_OP_SIZE; X+ unsigned int rotators = (l >> OP_SH_VFPU_ROT) & OP_MASK_VFPU_ROT; X+ unsigned int opsize, rothi, rotlo, negation, i; X+ X+ /* Determine the operand size so we'll know how many elements to output. */ X+ if (opcode == VFPU_OP_SIZE_PAIR) X+ opsize = 2; X+ else if (opcode == VFPU_OP_SIZE_TRIPLE) X+ opsize = 3; X+ else X+ opsize = (opcode == VFPU_OP_SIZE_QUAD) * 4; /* Sanity check. */ X+ X+ rothi = (rotators >> VFPU_SH_ROT_HI) & VFPU_MASK_ROT_HI; X+ rotlo = (rotators >> VFPU_SH_ROT_LO) & VFPU_MASK_ROT_LO; X+ negation = (rotators >> VFPU_SH_ROT_NEG) & VFPU_MASK_ROT_NEG; X+ X+ if (rothi == rotlo) X+ { X+ if (negation) X+ { X+ elements[0] = "-s"; X+ elements[1] = "-s"; X+ elements[2] = "-s"; X+ elements[3] = "-s"; X+ } X+ else X+ { X+ elements[0] = "s"; X+ elements[1] = "s"; X+ elements[2] = "s"; X+ elements[3] = "s"; X+ } X+ } X+ else X+ { X+ elements[0] = "0"; X+ elements[1] = "0"; X+ elements[2] = "0"; X+ elements[3] = "0"; X+ } X+ if (negation) X+ elements[rothi] = "-s"; X+ else X+ elements[rothi] = "s"; X+ elements[rotlo] = "c"; X+ X+ (*info->fprintf_func) (info->stream, "["); X+ i = 0; X+ for (;;) X+ { X+ (*info->fprintf_func) (info->stream, "%s", X+ elements[i++]); X+ if (i >= opsize) X+ break; X+ (*info->fprintf_func) (info->stream, ","); X+ } X+ (*info->fprintf_func) (info->stream, "]"); X+ } X+ break; X+ X+ case 'd': X+ case 'm': X+ case 'n': X+ case 's': X+ case 't': X+ case 'v': X+ case 'x': X+ { X+ unsigned int vreg = 0; X+ X+ /* The first char specifies the bitfield that contains the register number. */ X+ switch (*d) X+ { X+ case 'd': X+ case 'v': X+ case 'x': X+ vreg = (l >> OP_SH_VFPU_VD) & OP_MASK_VFPU_VD; X+ break; X+ X+ case 'm': X+ /* Combine bits 0-4 of vt with bits 5-6 of vt. */ X+ vreg = ((l >> OP_SH_VFPU_VT_LO) & OP_MASK_VFPU_VT_LO) X+ | ((l & OP_MASK_VFPU_VT_HI2) << OP_SH_VFPU_VT_HI); X+ break; X+ X+ case 'n': X+ /* Combine bits 0-4 of vt with bit 5 of vt. */ X+ vreg = ((l >> OP_SH_VFPU_VT_LO) & OP_MASK_VFPU_VT_LO) X+ | ((l & OP_MASK_VFPU_VT_HI1) << OP_SH_VFPU_VT_HI); X+ break; X+ X+ case 's': X+ { X+ unsigned int temp_vreg = l >> OP_SH_VFPU_VS; X+ X+ vreg = temp_vreg & OP_MASK_VFPU_VS; X+ if ((l & VFPU_OP_VT_VS_VD) == VFPU_OPCODE_VMMUL) X+ { X+ /* vmmul instructions have the RXC bit (bit 13) inverted. */ X+ if (temp_vreg & 0x20) X+ vreg = temp_vreg & 0x5f; X+ else X+ vreg |= 0x20; X+ } X+ } X+ break; X+ X+ case 't': X+ vreg = (l >> OP_SH_VFPU_VT) & OP_MASK_VFPU_VT; X+ break; X+ } X+ X+ /* The next char is the register set vreg comes from. */ X+ d++; X+ switch (*d) X+ { X+ case '0': X+ (*info->fprintf_func) (info->stream, "%s.s", X+ vfpu_sreg_names[vreg]); X+ break; X+ X+ case '1': X+ (*info->fprintf_func) (info->stream, "%s.p", X+ vfpu_vpreg_names[vreg]); X+ break; X+ X+ case '2': X+ (*info->fprintf_func) (info->stream, "%s.t", X+ vfpu_vtreg_names[vreg]); X+ break; X+ X+ case '3': X+ (*info->fprintf_func) (info->stream, "%s.q", X+ vfpu_vqreg_names[vreg]); X+ break; X+ X+ case '5': X+ (*info->fprintf_func) (info->stream, "%s.p", X+ vfpu_mpreg_names[vreg]); X+ break; X+ X+ case '6': X+ (*info->fprintf_func) (info->stream, "%s.t", X+ vfpu_mtreg_names[vreg]); X+ break; X+ X+ case '7': X+ (*info->fprintf_func) (info->stream, "%s.q", X+ vfpu_mqreg_names[vreg]); X+ break; X+ X+ default: X+ /* xgettext:c-format */ X+ (*info->fprintf_func) (info->stream, X+ _("# internal error, undefined vreg modifier(%c)"), X+ *d); X+ break; X+ } X+ X+ /* The last char is unused for disassembly. */ X+ d++; X+ } X+ break; X+ X+ case 'z': X+ (*info->fprintf_func) (info->stream, "%s", X+ vfpu_rwb_names[(l >> OP_SH_VFPU_RWB) & OP_MASK_VFPU_RWB]); X+ break; X+ } X+ break; X+ X default: X /* xgettext:c-format */ X (*info->fprintf_func) (info->stream, END-of-psptoolchain-binutils/files/patch-opcodes-mips-dis.c echo x - psptoolchain-binutils/files/patch-bfd-configure sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-configure << 'END-of-psptoolchain-binutils/files/patch-bfd-configure' X--- bfd/configure.orig 2009-02-26 14:37:44.000000000 +0100 X+++ bfd/configure 2009-02-26 14:38:23.000000000 +0100 X@@ -4366,8 +4366,8 @@ X bfdlibdir='$(libdir)' X bfdincludedir='$(includedir)' X if test "${host}" != "${target}"; then X- bfdlibdir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/lib' X- bfdincludedir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/include' X+ bfdlibdir='$(exec_prefix)/$(target_noncanonical)/lib' X+ bfdincludedir='$(exec_prefix)/$(target_noncanonical)/include' X fi X X END-of-psptoolchain-binutils/files/patch-bfd-configure echo x - psptoolchain-binutils/files/patch-bfd-archures.c sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-archures.c << 'END-of-psptoolchain-binutils/files/patch-bfd-archures.c' X--- bfd/archures.c.orig 2005-01-17 14:08:03.000000000 +0000 X+++ bfd/archures.c 2006-05-09 02:55:36.000000000 +0100 X@@ -155,6 +155,7 @@ X .#define bfd_mach_mips16 16 X .#define bfd_mach_mips5 5 X .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *} X+.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *} X .#define bfd_mach_mipsisa32 32 X .#define bfd_mach_mipsisa32r2 33 X .#define bfd_mach_mipsisa64 64 END-of-psptoolchain-binutils/files/patch-bfd-archures.c echo x - psptoolchain-binutils/files/patch-bfd-bfd-in2.h sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-bfd-in2.h << 'END-of-psptoolchain-binutils/files/patch-bfd-bfd-in2.h' X--- bfd/bfd-in2.h.orig 2005-03-02 21:23:20.000000000 +0000 X+++ bfd/bfd-in2.h 2006-05-09 02:55:36.000000000 +0100 X@@ -1600,6 +1600,7 @@ X #define bfd_mach_mips16 16 X #define bfd_mach_mips5 5 X #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ X+#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */ X #define bfd_mach_mipsisa32 32 X #define bfd_mach_mipsisa32r2 33 X #define bfd_mach_mipsisa64 64 END-of-psptoolchain-binutils/files/patch-bfd-bfd-in2.h echo x - psptoolchain-binutils/files/patch-bfd-elfxx-mips.c sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-elfxx-mips.c << 'END-of-psptoolchain-binutils/files/patch-bfd-elfxx-mips.c' X--- bfd/elfxx-mips.c.orig 2005-05-28 22:58:29.000000000 +0100 X+++ bfd/elfxx-mips.c 2006-05-09 02:55:36.000000000 +0100 X@@ -4669,6 +4669,9 @@ X case E_MIPS_MACH_SB1: X return bfd_mach_mips_sb1; X X+ case E_MIPS_MACH_ALLEGREX: X+ return bfd_mach_mips_allegrex; X+ X default: X switch (flags & EF_MIPS_ARCH) X { X@@ -7941,6 +7944,10 @@ X val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1; X break; X X+ case bfd_mach_mips_allegrex: X+ val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX; X+ break; X+ X case bfd_mach_mipsisa32: X val = E_MIPS_ARCH_32; X break; X@@ -8422,6 +8429,8 @@ X if (dynobj != NULL && force_local && h->root.type != STT_TLS) X { X got = mips_elf_got_section (dynobj, FALSE); X+ if (got) X+ { X g = mips_elf_section_data (got)->u.got_info; X X if (g->next) X@@ -8472,6 +8481,7 @@ X g->global_gotno--; X } X } X+ } X X _bfd_elf_link_hash_hide_symbol (info, &h->root, force_local); X } X@@ -9641,6 +9651,7 @@ X /* MIPS II extensions. */ X { bfd_mach_mips4000, bfd_mach_mips6000 }, X { bfd_mach_mipsisa32, bfd_mach_mips6000 }, X+ { bfd_mach_mips_allegrex, bfd_mach_mips6000 }, X X /* MIPS I extensions. */ X { bfd_mach_mips6000, bfd_mach_mips3000 }, END-of-psptoolchain-binutils/files/patch-bfd-elfxx-mips.c echo x - psptoolchain-binutils/files/patch-bfd-Makefile.in sed 's/^X//' >psptoolchain-binutils/files/patch-bfd-Makefile.in << 'END-of-psptoolchain-binutils/files/patch-bfd-Makefile.in' X--- bfd/Makefile.in.orig 2005-06-12 19:58:55.000000000 +0100 X+++ bfd/Makefile.in 2006-05-09 02:55:36.000000000 +0100 X@@ -250,7 +250,7 @@ X AUTOMAKE_OPTIONS = 1.9 cygnus X X # Uncomment the following line when doing a release. X-RELEASE=y X+#RELEASE=y X INCDIR = $(srcdir)/../include X CSEARCH = -I. -I$(srcdir) -I$(INCDIR) X MKDEP = gcc -MM END-of-psptoolchain-binutils/files/patch-bfd-Makefile.in echo x - psptoolchain-binutils/files/patch-binutils-readelf.c sed 's/^X//' >psptoolchain-binutils/files/patch-binutils-readelf.c << 'END-of-psptoolchain-binutils/files/patch-binutils-readelf.c' X--- binutils/readelf.c.orig 2005-04-20 19:43:36.000000000 +0100 X+++ binutils/readelf.c 2006-05-09 02:55:36.000000000 +0100 X@@ -2043,6 +2043,7 @@ X case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break; X case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break; X case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break; X+ case E_MIPS_MACH_ALLEGREX: strcat (buf, ", allegrex"); break; X case 0: X /* We simply ignore the field in this case to avoid confusion: X MIPS ELF does not specify EF_MIPS_MACH, it is a GNU END-of-psptoolchain-binutils/files/patch-binutils-readelf.c echo x - psptoolchain-binutils/files/patch-gas-config-tc-mips.c sed 's/^X//' >psptoolchain-binutils/files/patch-gas-config-tc-mips.c << 'END-of-psptoolchain-binutils/files/patch-gas-config-tc-mips.c' X--- gas/config/tc-mips.c.orig 2005-06-12 19:07:03.000000000 +0100 X+++ gas/config/tc-mips.c 2006-05-09 02:55:36.000000000 +0100 X@@ -92,6 +92,32 @@ X X #define ZERO 0 X #define AT 1 X+#define V0 2 X+#define V1 3 X+#define A0 4 X+#define A1 5 X+#define A2 6 X+#define A3 7 X+#define T0 8 X+#define T1 9 X+#define T2 10 X+#define T3 11 X+#define T4 12 X+#define T5 13 X+#define T6 14 X+#define T7 15 X+#define S0 16 X+#define S1 17 X+#define S2 18 X+#define S3 19 X+#define S4 20 X+#define S5 21 X+#define S6 22 X+#define S7 23 X+#define T8 24 X+#define T9 25 X+#define K0 26 X+#define K1 27 X #define TREG 24 X #define PIC_CALL_REG 25 X #define KT0 26 X@@ -365,11 +391,15 @@ X #define CPU_HAS_MDMX(cpu) (FALSE \ X ) X X+/* True if the given CPU belongs to the Allegrex family. */ X+#define CPU_IS_ALLEGREX(CPU) ((CPU) == CPU_ALLEGREX \ X+ ) X+ X /* True if CPU has a dror instruction. */ X #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) X X /* True if CPU has a ror instruction. */ X-#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) X+#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) || CPU_IS_ALLEGREX (CPU) X X /* True if mflo and mfhi can be immediately followed by instructions X which write to the HI and LO registers. X@@ -393,6 +423,7 @@ X || mips_opts.arch == CPU_R12000 \ X || mips_opts.arch == CPU_RM7000 \ X || mips_opts.arch == CPU_VR5500 \ X+ || mips_opts.arch == CPU_ALLEGREX \ X ) X X /* Whether the processor uses hardware interlocks to protect reads X@@ -1142,6 +1173,8 @@ X static expressionS imm_expr; X static expressionS imm2_expr; X static expressionS offset_expr; X+static expressionS vimm_expr[4]; X+static expressionS voffset_expr[4]; X X /* Relocs associated with imm_expr and offset_expr. */ X X@@ -1150,6 +1183,15 @@ X static bfd_reloc_code_real_type offset_reloc[3] X = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; X X+/* set by vfpu code for prefix instructions */ X+ X+static bfd_boolean vfpu_dprefix; X+static char vfpu_dprefix_str[64]; X+static bfd_boolean vfpu_sprefix; X+static char vfpu_sprefix_str[64]; X+static bfd_boolean vfpu_tprefix; X+static char vfpu_tprefix_str[64]; X+ X /* These are set by mips16_ip if an explicit extension is used. */ X X static bfd_boolean mips16_small, mips16_ext; X@@ -1641,6 +1683,62 @@ X return; X } X X+ /* If we've generated operands for a VFPU prefix instruction then we need X+ to assemble and append the prefix instruction before emitting the X+ instruction it prefixes. Note that in mips_ip prefix operands do not X+ cause any side effects with imm_expr or offset_expr. If they did X+ we'd have to save and restore them here. */ X+ if (CPU_IS_ALLEGREX (mips_opts.arch) && ((vfpu_dprefix || vfpu_sprefix || vfpu_tprefix))) X+ { X+ X+ if (mips_opts.noreorder X+ && ( history[0].insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY X+ | INSN_COND_BRANCH_DELAY X+ | INSN_COND_BRANCH_LIKELY))) X+ { X+ as_bad (_("instruction with prefix cannot be used in branch delay slot")); X+ } X+ X+ if (vfpu_dprefix) X+ { X+ struct mips_cl_insn prefix; X+ bfd_reloc_code_real_type unused_reloc[3] X+ = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; X+ char buf[256]; X+ X+ sprintf (buf, "vpfxd %s", vfpu_dprefix_str); X+ mips_ip (buf, &prefix); X+ append_insn (&prefix, NULL, unused_reloc); X+ vfpu_dprefix = FALSE; X+ } X+ X+ if (vfpu_sprefix) X+ { X+ struct mips_cl_insn prefix; X+ bfd_reloc_code_real_type unused_reloc[3] X+ = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; X+ char buf[256]; X+ X+ sprintf (buf, "vpfxs %s", vfpu_sprefix_str); X+ mips_ip (buf, &prefix); X+ append_insn ( &prefix, NULL, unused_reloc); X+ vfpu_sprefix = FALSE; X+ } X+ X+ if (vfpu_tprefix) X+ { X+ struct mips_cl_insn prefix; X+ bfd_reloc_code_real_type unused_reloc[3] X+ = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; X+ char buf[256]; X+ X+ sprintf (buf, "vpfxt %s", vfpu_tprefix_str); X+ mips_ip (buf, &prefix); X+ append_insn (&prefix, NULL, unused_reloc); X+ vfpu_tprefix = FALSE; X+ } X+ } X+ X if (insn.insn_mo->pinfo == INSN_MACRO) X { X macro_start (); X@@ -3128,6 +3226,55 @@ X insn.insn_opcode |= va_arg (args, unsigned long); X continue; X X+ /* VFPU fields */ X+ case '?': X+ switch (*fmt++) X+ { X+ case 'o': X+ *r = (bfd_reloc_code_real_type) va_arg (args, int); X+ assert (*r == BFD_RELOC_GPREL16 X+ || *r == BFD_RELOC_MIPS_LITERAL X+ || *r == BFD_RELOC_MIPS_HIGHER X+ || *r == BFD_RELOC_HI16_S X+ || *r == BFD_RELOC_LO16 X+ || *r == BFD_RELOC_MIPS_GOT16 X+ || *r == BFD_RELOC_MIPS_CALL16 X+ || *r == BFD_RELOC_MIPS_GOT_DISP X+ || *r == BFD_RELOC_MIPS_GOT_PAGE X+ || *r == BFD_RELOC_MIPS_GOT_OFST X+ || *r == BFD_RELOC_MIPS_GOT_LO16 X+ || *r == BFD_RELOC_MIPS_CALL_LO16); X+ break; X+ case 'd': X+ insn.insn_opcode |= va_arg (args, int) << VF_SH_VD; X+ fmt += 2; X+ break; X+ case 's': X+ insn.insn_opcode |= va_arg (args, int) << VF_SH_VS; X+ fmt += 2; X+ break; X+ case 'm': X+ { X+ int vtreg = va_arg (args, int); X+ insn.insn_opcode |= (vtreg & VF_MASK_VML) << VF_SH_VML; X+ insn.insn_opcode |= ((vtreg >> 5) & VF_MASK_VMH) << VF_SH_VMH; X+ fmt += 2; X+ } X+ break; X+ case 'n': X+ { X+ int vtreg = va_arg (args, int); X+ insn.insn_opcode |= (vtreg & VF_MASK_VNL) << VF_SH_VNL; X+ insn.insn_opcode |= ((vtreg >> 5) & VF_MASK_VNH) << VF_SH_VNH; X+ fmt += 2; X+ } X+ break; X+ case 'e': X+ insn.insn_opcode |= va_arg (args, int) << VF_SH_MCOND; X+ break; X+ } X+ continue; X+ X default: X internalError (); X } X@@ -4103,6 +4250,7 @@ X macro (struct mips_cl_insn *ip) X { X register int treg, sreg, dreg, breg; X+ int vsreg, vtreg, vdreg, vmreg, vwb; X int tempreg; X int mask; X int used_at = 0; X@@ -4128,6 +4276,13 @@ X sreg = breg = (ip->insn_opcode >> 21) & 0x1f; X mask = ip->insn_mo->mask; X X+ vmreg = ((ip->insn_opcode >> 16) & 0x1f) X+ | ((ip->insn_opcode << 5) & 0x60); X+ vtreg = (ip->insn_opcode >> 16) & 0x7f; X+ vsreg = (ip->insn_opcode >> 8) & 0x7f; X+ vdreg = (ip->insn_opcode >> 0) & 0x7f; X+ vwb = (ip->insn_opcode >> 1) & 0x1; X+ X expr1.X_op = O_constant; X expr1.X_op_symbol = NULL; X expr1.X_add_symbol = NULL; X@@ -5654,6 +5809,26 @@ X /* Itbl support may require additional care here. */ X coproc = 1; X goto ld; X+ case M_LV_S_AB: X+ s = "lv.s"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto ld; X+ case M_LV_Q_AB: X+ s = "lv.q"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto ld; X+ case M_LVL_Q_AB: X+ s = "lvl.q"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto ld; X+ case M_LVR_Q_AB: X+ s = "lvr.q"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto ld; X case M_LWL_AB: X s = "lwl"; X lr = 1; X@@ -5738,6 +5913,29 @@ X /* Itbl support may require additional care here. */ X coproc = 1; X goto st; X+ case M_SV_S_AB: X+ s = "sv.s"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto st; X+ case M_SV_Q_AB: X+ if (vwb) X+ s = "vwb.q"; X+ else X+ s = "sv.q"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto st; X+ case M_SVL_Q_AB: X+ s = "svl.q"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto st; X+ case M_SVR_Q_AB: X+ s = "svr.q"; X+ /* Itbl support may require additional care here. */ X+ coproc = 1; X+ goto st; X case M_SWL_AB: X s = "swl"; X goto st; X@@ -5787,6 +5985,22 @@ X || mask == M_L_DAB X || mask == M_S_DAB) X fmt = "T,o(b)"; X+ else if (mask == M_LV_S_AB X+ || mask == M_SV_S_AB) X+ { X+ fmt = "?m0x,?o(b)"; X+ treg = vmreg; X+ } X+ else if (mask == M_LV_Q_AB X+ || mask == M_SV_Q_AB X+ || mask == M_LVL_Q_AB X+ || mask == M_LVR_Q_AB X+ || mask == M_SVL_Q_AB X+ || mask == M_SVR_Q_AB) X+ { X+ fmt = "?n3x,?o(b)"; X+ treg = vmreg; X+ } X else if (coproc) X fmt = "E,o(b)"; X else X@@ -6150,6 +6364,138 @@ X break; X } X X+ case M_LVI_S_SS: X+ case M_LVI_P_SS: X+ case M_LVI_T_SS: X+ case M_LVI_Q_SS: X+ { X+ int mtx = (vtreg >> VF_SH_MR_MTX) & VF_MASK_MR_MTX; X+ int idx = (vtreg >> VF_SH_MR_IDX) & VF_MASK_MR_IDX; X+ int fsl = 0; X+ int rxc = 0; X+ int vtreg_s = 0; X+ int vnum = 0; X+ int vat = 0; X+ int i; X+ X+ switch (mask) X+ { X+ case M_LVI_S_SS: X+ vnum = 1; X+ fsl = (vtreg >> VF_SH_MR_FSL) & VF_MASK_MR_FSL; X+ rxc = 0; X+ break; X+ case M_LVI_P_SS: X+ vnum = 2; X+ fsl = ((vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL) << 1; X+ rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC; X+ break; X+ case M_LVI_T_SS: X+ vnum = 3; X+ fsl = (vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL; X+ rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC; X+ break; X+ case M_LVI_Q_SS: X+ vnum = 4; X+ fsl = 0; X+ rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC; X+ break; X+ } X+ if (rxc) X+ vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_FSL) X+ | (fsl << VF_SH_MR_IDX); X+ else X+ vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_IDX) X+ | (fsl << VF_SH_MR_FSL); X+ X+ for (i = 0; i < vnum; i++) { X+ imm_expr = vimm_expr[i]; X+ offset_expr = voffset_expr[i]; X+ X+ if (imm_expr.X_op == O_constant) X+ { X+ load_register (AT, &imm_expr, 0); X+ macro_build ((expressionS *) NULL, X+ "mtv", "t,?d0z", AT, vtreg_s); X+ vat = 1; X+ } X+ else X+ { X+ assert (offset_expr.X_op == O_symbol X+ && strcmp (segment_name (S_GET_SEGMENT X+ (offset_expr.X_add_symbol)), X+ ".lit4") == 0 X+ && offset_expr.X_add_number == 0); X+ macro_build (&offset_expr, X+ "lv.s", "?m0x,?o(b)", vtreg_s, X+ (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); X+ } X+ X+ if (rxc) X+ vtreg_s += (1 << VF_SH_MR_IDX); X+ else X+ vtreg_s += (1 << VF_SH_MR_FSL); X+ } X+ X+ if (vat) X+ break; X+ else X+ return; X+ } X+ X+ case M_LVHI_S_SS: X+ case M_LVHI_P_SS: X+ { X+ int mtx = (vtreg >> VF_SH_MR_MTX) & VF_MASK_MR_MTX; X+ int idx = (vtreg >> VF_SH_MR_IDX) & VF_MASK_MR_IDX; X+ int fsl = 0; X+ int rxc = 0; X+ int vtreg_s = 0; X+ int vnum = 0; X+ int i; X+ unsigned int f16v; X+ char f16v_str[16]; X+ X+ switch (mask) X+ { X+ case M_LVHI_S_SS: X+ vnum = 2; X+ fsl = (vtreg >> VF_SH_MR_FSL) & VF_MASK_MR_FSL; X+ rxc = 0; X+ break; X+ case M_LVHI_P_SS: X+ vnum = 4; X+ fsl = ((vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL) << 1; X+ rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC; X+ break; X+ } X+ if (rxc) X+ vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_FSL) X+ | (fsl << VF_SH_MR_IDX); X+ else X+ vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_IDX) X+ | (fsl << VF_SH_MR_FSL); X+ X+ X+ for (i = 0; i < vnum; i += 2) { X+ f16v = ((vimm_expr[i + 1].X_add_number & 0xffff) << 16) X+ | (vimm_expr[i].X_add_number & 0xffff); X+ sprintf(f16v_str, "0x%08x", f16v); X+ my_getExpression (&imm_expr, f16v_str); X+ X+ load_register (AT, &imm_expr, 0); X+ macro_build ((expressionS *) NULL, X+ "mtv", "t,?d0z", AT, vtreg_s); X+ X+ if (rxc) X+ vtreg_s += (1 << VF_SH_MR_IDX); X+ else X+ vtreg_s += (1 << VF_SH_MR_FSL); X+ } X+ X+ break; X+ } X+ X case M_LI_D: X /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits X wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high X@@ -6672,6 +7018,27 @@ X move_register (dreg, sreg); X break; X X+ case M_VCMOV_S: X+ s = "vcmovt.s"; X+ fmt = "?d0d,?s0s,?e"; X+ goto vcmov; X+ case M_VCMOV_P: X+ s = "vcmovt.p"; X+ fmt = "?d1d,?s1s,?e"; X+ goto vcmov; X+ case M_VCMOV_T: X+ s = "vcmovt.t"; X+ fmt = "?d2d,?s2s,?e"; X+ goto vcmov; X+ case M_VCMOV_Q: X+ s = "vcmovt.q"; X+ fmt = "?d3d,?s3s,?e"; X+ vcmov: X+ macro_build ((expressionS *) NULL, s, fmt, X+ vdreg, vsreg, X+ (ip->insn_opcode >> VF_SH_MCOND) & VF_MASK_MCOND); X+ return; X+ X #ifdef LOSING_COMPILER X default: X /* Try and see if this is a new itbl instruction. X@@ -7348,6 +7715,39 @@ X move_register (treg, tempreg); X break; X X+ case M_ULV_S: X+ if (mips_opts.arch == CPU_ALLEGREX) X+ as_bad (_("opcode not supported on this processor")); X+ off = 3; X+ if (offset_expr.X_add_number >= 0x8000 - off) X+ as_bad (_("operand overflow")); X+ if (! target_big_endian) X+ offset_expr.X_add_number += off; X+ macro_build (&offset_expr, "lwl", "t,o(b)", X+ AT, (int) BFD_RELOC_LO16, breg); X+ if (! target_big_endian) X+ offset_expr.X_add_number -= off; X+ else X+ offset_expr.X_add_number += off; X+ macro_build (&offset_expr, "lwr", "t,o(b)", X+ AT, (int) BFD_RELOC_LO16, breg); X+ X+ macro_build ((expressionS *) NULL, "mtv", "t,?d0z", X+ AT, vmreg); X+ break; X+ X+ case M_ULV_Q: X+ off = 12; X+ if (offset_expr.X_add_number >= 0x8000 - off) X+ as_bad (_("operand overflow")); X+ offset_expr.X_add_number += off; X+ macro_build (&offset_expr, "lvl.q", "?n3x,?o(b)", X+ vmreg, (int) BFD_RELOC_LO16, breg); X+ offset_expr.X_add_number -= off; X+ macro_build (&offset_expr, "lvr.q", "?n3x,?o(b)", X+ vmreg, (int) BFD_RELOC_LO16, breg); X+ return; X+ X case M_ULD_A: X s = "ldl"; X s2 = "ldr"; X@@ -7430,6 +7830,55 @@ X macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); X break; X X+ case M_USV_S: X+ off = 3; X+ if (offset_expr.X_add_number >= 0x8000 - off) X+ as_bad (_("operand overflow")); X+ macro_build ((expressionS *) NULL, "mfv", "t,?d0z", X+ AT, vmreg); X+ if (mips_opts.arch != CPU_ALLEGREX) X+ { X+ if (! target_big_endian) X+ offset_expr.X_add_number += off; X+ macro_build (&offset_expr, "swl", "t,o(b)", X+ AT, (int) BFD_RELOC_LO16, breg); X+ if (! target_big_endian) X+ offset_expr.X_add_number -= off; X+ else X+ offset_expr.X_add_number += off; X+ macro_build (&offset_expr, "swr", "t,o(b)", X+ AT, (int) BFD_RELOC_LO16, breg); X+ } X+ else X+ { X+ if (target_big_endian) X+ offset_expr.X_add_number += off; X+ while (off-- >= 0) X+ { X+ macro_build (&offset_expr, "sb", "t,o(b)", X+ AT, (int) BFD_RELOC_LO16, breg); X+ macro_build ((expressionS *) NULL, "ror", X+ "d,w,<", AT, AT, 8); X+ if (target_big_endian) X+ --offset_expr.X_add_number; X+ else X+ ++offset_expr.X_add_number; X+ } X+ } X+ break; X+ X+ case M_USV_Q: X+ off = 12; X+ if (offset_expr.X_add_number >= 0x8000 - off) X+ as_bad (_("operand overflow")); X+ offset_expr.X_add_number += off; X+ macro_build (&offset_expr, "svl.q", "?n3x,?o(b)", X+ vmreg, (int) BFD_RELOC_LO16, breg); X+ offset_expr.X_add_number -= off; X+ macro_build (&offset_expr, "svr.q", "?n3x,?o(b)", X+ vmreg, (int) BFD_RELOC_LO16, breg); X+ return; X+ X case M_USD_A: X s = "sdl"; X s2 = "sdr"; X@@ -7817,6 +8266,103 @@ X case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; X case '[': break; X case ']': break; X+ X+ /* VFPU fields */ X+ case '?': X+ switch (c = *p++) X+ { X+ case '[': break; X+ case ']': break; X+ case 'y': X+ { X+ if ((*p != '0') && (*p != '1') && (*p != '2') && (*p != '3')) X+ { X+ as_bad (_("internal: bad mips opcode : %s %s"), X+ opc->name, opc->args); X+ return 0; X+ } X+ p++; X+ } X+ break; X+ X+ case 'o': USE_BITS (VF_MASK_OFFSET, VF_SH_OFFSET); break; X+ X+ case 's': X+ case 't': X+ case 'd': X+ case 'v': X+ case 'x': X+ case 'm': X+ case 'n': X+ { X+ if ((*p != '0') && (*p != '1') && (*p != '2') && (*p != '3') X+ && (*p != '5') && (*p != '6') && (*p != '7')) X+ { X+ as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"), X+ *p, opc->name, opc->args); X+ return 0; X+ } X+ p++; X+ X+ if ((*p != 's') && (*p != 't') && (*p != 'd') X+ && (*p != 'y') && (*p != 'x') && (*p != 'z') X+ && (*p != 'w') && (*p != 'm')) X+ { X+ as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"), X+ *(p - 1), opc->name, opc->args); X+ } X+ p++; X+ X+ switch (c) X+ { X+ case 's': USE_BITS (VF_MASK_VS, VF_SH_VS); break; X+ case 't': USE_BITS (VF_MASK_VT, VF_SH_VT); break; X+ case 'd': X+ case 'v': X+ case 'x': USE_BITS (VF_MASK_VD, VF_SH_VD); break; X+ case 'm': USE_BITS (VF_MASK_VML, VF_SH_VML); X+ USE_BITS (VF_MASK_VMH, VF_SH_VMH); break; X+ case 'n': USE_BITS (VF_MASK_VNL, VF_SH_VNL); X+ USE_BITS (VF_MASK_VNH, VF_SH_VNH); break; X+ } X+ } X+ break; X+ X+ case 'f': USE_BITS (VF_MASK_CC, VF_SH_CC); X+ p++; break; X+ X+ case 'a': USE_BITS (VF_MASK_CONST, VF_SH_CONST); break; X+ case 'b': USE_BITS (VF_MASK_SCALE, VF_SH_SCALE); break; X+ case 'c': USE_BITS (VF_MASK_BCOND, VF_SH_BCOND); break; X+ case 'e': USE_BITS (VF_MASK_MCOND, VF_SH_MCOND); break; X+ X+ case 'i': USE_BITS (VF_MASK_WRAP, VF_SH_WRAP); break; X+ X+ case 'q': USE_BITS (VF_MASK_VCD, VF_SH_VCD); break; X+ case 'r': USE_BITS (VF_MASK_VCS, VF_SH_VCS); break; X+ X+ case 'u': USE_BITS (VF_MASK_HFLOAT, VF_SH_HFLOAT); break; X+ X+ case 'w': USE_BITS (VF_MASK_ROT, VF_SH_ROT); break; X+ case 'z': USE_BITS (VF_MASK_RWB, VF_SH_RWB); break; X+ X+ case '0': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '1': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '2': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '3': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '4': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '5': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '6': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ case '7': USE_BITS (VF_MASK_PFX, VF_SH_PFX); break; X+ X+ default: X+ as_bad (_("internal: bad mips opcode (unknown extension operand type `?%c'): %s %s"), X+ c, opc->name, opc->args); X+ return 0; X+ X+ } X+ break; X+ X default: X as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), X c, opc->name, opc->args); X@@ -7845,12 +8391,15 @@ X char c = 0; X struct mips_opcode *insn; X char *argsStart; X- unsigned int regno; X+ unsigned int regno = 0; X unsigned int lastregno = 0; X unsigned int lastpos = 0; X unsigned int limlo, limhi; X char *s_reset; X char save_c = 0; X+ unsigned int vdregno = 0xffff; X+ char vdregt = 0; X+ char vdregl = 0; X X insn_error = NULL; X X@@ -8238,26 +8787,1171 @@ X s = expr_end; X continue; X X- case 'b': /* base register */ X- case 'd': /* destination register */ X- case 's': /* source register */ X- case 't': /* target register */ X- case 'r': /* both target and source */ X- case 'v': /* both dest and source */ X- case 'w': /* both dest and target */ X- case 'E': /* coprocessor target register */ X- case 'G': /* coprocessor destination register */ X- case 'K': /* 'rdhwr' destination register */ X- case 'x': /* ignore register name */ X- case 'z': /* must be zero register */ X- case 'U': /* destination register (clo/clz). */ X- s_reset = s; X- if (s[0] == '$') X+ /* VFPU fields */ X+ case '?': X+ switch (*++args) X { X+ case '[': X+ case ']': X+ if (*s++ == *args) X+ continue; X+ break; X X- if (ISDIGIT (s[1])) X- { X- ++s; X+ case 'y': /* immediate separator */ X+ ++args; X+ vimm_expr[*args - '0'] = imm_expr; X+ voffset_expr[*args - '0'] = offset_expr; X+ X+ imm_expr.X_op = O_absent; X+ offset_expr.X_op = O_absent; X+ imm_reloc[0] = BFD_RELOC_UNUSED; X+ imm_reloc[1] = BFD_RELOC_UNUSED; X+ imm_reloc[2] = BFD_RELOC_UNUSED; X+ offset_reloc[0] = BFD_RELOC_UNUSED; X+ offset_reloc[1] = BFD_RELOC_UNUSED; X+ offset_reloc[2] = BFD_RELOC_UNUSED; X+ X+ continue; X+ X+ case 'o': /* 16 bit offset */ X+ /* Check whether there is only a single bracketed expression X+ left. If so, it must be the base register and the X+ constant must be zero. */ X+ if (*s == '(' && strchr (s + 1, '(') == 0) X+ { X+ offset_expr.X_op = O_constant; X+ offset_expr.X_add_number = 0; X+ continue; X+ } X+ X+ /* If this value won't fit into a 16 bit offset, then go X+ find a macro that will generate the 32 bit offset X+ code pattern. */ X+ if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 X+ && (offset_expr.X_op != O_constant X+ || offset_expr.X_add_number >= 0x8000 X+ || offset_expr.X_add_number < -0x8000)) X+ break; X+ X+ s = expr_end; X+ continue; X+ X+ case 's': /* VFPU source register */ X+ case 't': /* VFPU target register */ X+ case 'd': /* VFPU destination register */ X+ case 'v': /* VFPU destination register */ X+ case 'x': /* VFPU destination register */ X+ case 'm': /* VFPU target regsiter (load/store) */ X+ case 'n': /* VFPU target regsiter (load/store) */ X+ { X+ int dtype_err = 0; X+ int dnum_err = 0; X+ int dlen = 0; X+ char dtype = s[0]; X+ char regtype = *(args + 1); X+ X+ int mtx = 0; X+ int idx = 0; X+ int rxc = 0; X+ int fsl = 0; X+ int vidx = 0; X+ int vfsl = 0; X+ X+ if (ISDIGIT (s[1])) X+ { X+ int num = 0; X+ s++; X+ do X+ { X+ num *= 10; X+ num += *s - '0'; X+ dlen++; X+ s++; X+ } X+ while (ISDIGIT (*s)); X+ X+ if ((s[0] == '.') X+ && (s[1] == 's' || s[1] == 'p' X+ || s[1] == 't' || s[1] == 'q')) X+ s += 2; X+ X+ if (ISUPPER(dtype)) X+ dtype -= 'A' - 'a'; X+ X+ if (dtype == '$') X+ { X+ regno = num; X+ if (regno > VF_MAX_MR) X+ as_bad (_("Invalid VFPU register number (%d)"), X+ regno); X+ X+ idx = (num >> VF_SH_MR_IDX) & VF_MASK_MR_IDX; X+ vfsl = (num >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL; X+ switch (regtype) X+ { X+ case '0': /* single word */ X+ break; X+ case '1': /* pare word */ X+ dnum_err = (vfsl & 0x1); X+ break; X+ case '2': /* triple word */ X+ dnum_err = (vfsl > 1); X+ break; X+ case '3': /* quad word */ X+ dnum_err = (vfsl > 0); X+ break; X+ case '5': /* 2x2 word */ X+ dnum_err = (vfsl & 0x1) || (idx & 0x1); X+ break; X+ case '6': /* 3x3 word */ X+ dnum_err = (vfsl > 1) || (idx > 1); X+ break; X+ case '7': /* 4x4 word */ X+ dnum_err = (vfsl > 0) || (idx > 0); X+ break; X+ } X+ X+ if (dnum_err) X+ as_bad (_("Improper VFPU register number (%d)"), X+ regno); X+ X+ } X+ else if ((dlen == 3) X+ && ((dtype == 's') X+ || (dtype == 'c') || (dtype == 'r') X+ || (dtype == 'm') || (dtype == 'e'))) X+ { X+ mtx = num / 100; X+ if ((dtype == 'r') || (dtype == 'e')) X+ { X+ vfsl = (num / 10) % 10; X+ vidx = num % 10; X+ rxc = 1; X+ } X+ else X+ { X+ vidx = (num / 10) % 10; X+ vfsl = num % 10; X+ rxc = 0; X+ } X+ X+ switch (regtype) X+ { X+ case '0': /* single word */ X+ idx = vidx; X+ fsl = vfsl; X+ dtype_err = (dtype != 's'); X+ break; X+ case '1': /* pare word */ X+ idx = vidx; X+ fsl = (vfsl & 0x2) | rxc; X+ dnum_err = (vfsl & 0x1); X+ dtype_err = (dtype != 'c') && (dtype != 'r'); X+ break; X+ case '2': /* triple word */ X+ idx = vidx; X+ fsl = ((vfsl & 0x1) << 1) | rxc; X+ dnum_err = (vfsl > 1); X+ dtype_err = (dtype != 'c') && (dtype != 'r'); X+ break; X+ case '3': /* quad word */ X+ idx = vidx; X+ fsl = rxc; X+ dnum_err = (vfsl > 0); X+ dtype_err = (dtype != 'c') && (dtype != 'r'); X+ break; X+ case '5': /* 2x2 word */ X+ idx = vidx & 0x2; X+ fsl = (vfsl & 0x2) | rxc; X+ dnum_err = (vfsl & 0x1) || (vidx & 0x1); X+ dtype_err = (dtype != 'm') && (dtype != 'e'); X+ break; X+ case '6': /* 3x3 word */ X+ idx = vidx & 0x1; X+ fsl = ((vfsl & 0x1) << 1) | rxc; X+ dnum_err = (vfsl > 1) || (vidx > 1); X+ dtype_err = (dtype != 'm') && (dtype != 'e'); X+ break; X+ case '7': /* 4x4 word */ X+ idx = 0; X+ fsl = rxc; X+ dnum_err = (vfsl > 0) || (vidx > 0); X+ dtype_err = (dtype != 'm') && (dtype != 'e'); X+ break; X+ } X+ X+ if (dtype_err) X+ as_bad (_("Improper VFPU register prefix '%c'"), X+ dtype); X+ if (dnum_err) X+ as_bad (_("Improper VFPU register number (%03d)"), X+ num); X+ X+ if (mtx > VF_MAX_MR_MTX) X+ as_bad (_("VFPU matrix range over %d"), mtx); X+ if (vidx > VF_MAX_MR_IDX) X+ as_bad (_("VFPU index range over %d"), idx); X+ if (vfsl > VF_MAX_MR_FSL) X+ as_bad (_("VFPU field select range over %d"), fsl); X+ X+ regno = ((fsl & VF_MASK_MR_FSL) << VF_SH_MR_FSL) X+ | ((mtx & VF_MASK_MR_MTX) << VF_SH_MR_MTX) X+ | ((idx & VF_MASK_MR_IDX) << VF_SH_MR_IDX); X+ } X+ else X+ { X+ as_bad (_("Improper VFPU register prefix '%c'"), X+ dtype); X+ } X+ } X+ else X+ { X+ as_bad (_("bad operand %s"), s); X+ } X+ X+ if ((*args == 'v') || (*args == 'x')) X+ { X+ vdregno = regno; X+ vdregt = regtype; X+ vdregl = (*args == 'v'); X+ } X+ else if (vdregno <= VF_MAX_MR) X+ { X+ static unsigned short used_vreg[8][16] = { X+ { 0x0001, 0x0010, 0x0100, 0x1000, X+ 0x0002, 0x0020, 0x0200, 0x2000, X+ 0x0004, 0x0040, 0x0400, 0x4000, X+ 0x0008, 0x0080, 0x0800, 0x8000 }, X+ { 0x0003, 0x0030, 0x0300, 0x3000, X+ 0x0011, 0x0022, 0x0044, 0x0088, X+ 0x000c, 0x00c0, 0x0c00, 0xc000, X+ 0x1100, 0x2200, 0x4400, 0x8800 }, X+ { 0x0007, 0x0070, 0x0700, 0x7000, X+ 0x0111, 0x0222, 0x0444, 0x0888, X+ 0x000e, 0x00e0, 0x0e00, 0xe000, X+ 0x1110, 0x2220, 0x4440, 0x8880 }, X+ { 0x000f, 0x00f0, 0x0f00, 0xf000, X+ 0x1111, 0x2222, 0x4444, 0x8888, X+ 0x000f, 0x00f0, 0x0f00, 0xf000, X+ 0x1111, 0x2222, 0x4444, 0x8888 }, X+ { 0x0000, 0x0000, 0x0000, 0x0000, X+ 0x0000, 0x0000, 0x0000, 0x0000, X+ 0x0000, 0x0000, 0x0000, 0x0000, X+ 0x0000, 0x0000, 0x0000, 0x0000 }, X+ { 0x0033, 0x0033, 0x3300, 0x3300, X+ 0x0033, 0x0033, 0x00cc, 0x00cc, X+ 0x00cc, 0x00cc, 0xcc00, 0xcc00, X+ 0x3300, 0x3300, 0xcc00, 0xcc00 }, X+ { 0x0777, 0x7770, 0x0777, 0x7770, X+ 0x0777, 0x0eee, 0x0777, 0x0eee, X+ 0x0eee, 0xeee0, 0x0eee, 0xeee0, X+ 0x7770, 0xeee0, 0x7770, 0xeee0 }, X+ { 0xffff, 0xffff, 0xffff, 0xffff, X+ 0xffff, 0xffff, 0xffff, 0xffff, X+ 0xffff, 0xffff, 0xffff, 0xffff, X+ 0xffff, 0xffff, 0xffff, 0xffff }, X+ }; X+ int dmtx, smtx; X+ int dfsl, sfsl; X+ int didx, sidx; X+ int drxc, srxc; X+ X+ dmtx = (vdregno >> VF_SH_MR_MTX) & VF_MASK_MR_MTX; X+ smtx = (regno >> VF_SH_MR_MTX) & VF_MASK_MR_MTX; X+ X+ if (dmtx == smtx) X+ { X+ unsigned short dused, sused; X+ int dtype, stype; X+ X+ dfsl = (vdregno >> VF_SH_MR_FSL) & VF_MASK_MR_FSL; X+ didx = (vdregno >> VF_SH_MR_IDX) & VF_MASK_MR_IDX; X+ drxc = (vdregno >> VF_SH_MR_RXC) & VF_MASK_MR_RXC; X+ sfsl = (regno >> VF_SH_MR_FSL) & VF_MASK_MR_FSL; X+ sidx = (regno >> VF_SH_MR_IDX) & VF_MASK_MR_IDX; X+ srxc = (regno >> VF_SH_MR_RXC) & VF_MASK_MR_RXC; X+ X+ dtype = vdregt - '0'; X+ stype = regtype - '0'; X+ dused = used_vreg[dtype][(dfsl << 2) + didx]; X+ sused = used_vreg[stype][(sfsl << 2) + sidx]; X+ X+ if ((dused & sused) X+ && (vdregl || (dused ^ sused) || (drxc != srxc))) X+ { X+ int dvfsl; X+ dvfsl = (vdregno >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL; X+ switch (vdregt) X+ { X+ case '1': X+ dvfsl <<= 1; X+ case '2': X+ case '3': X+ if (drxc) X+ as_bad (_("VFPU register conflict(R%d%d%d)"), X+ dmtx, dvfsl, didx); X+ else X+ as_bad (_("VFPU register conflict(C%d%d%d)"), X+ dmtx, didx, dvfsl); X+ break; X+ case '5': X+ dvfsl <<= 1; X+ case '6': X+ case '7': X+ if (drxc) X+ as_bad (_("VFPU register conflict(E%d%d%d)"), X+ dmtx, dvfsl, didx); X+ else X+ as_bad (_("VFPU register conflict(M%d%d%d)"), X+ dmtx, didx, dvfsl); X+ break; X+ } X+ } X+ } X+ } X+ X+ switch (*args++) X+ { X+ case 's': X+ if ( X+ (ip->insn_opcode X+ & VFPU_MASK_RPT_MMUL) == VFPU_INST_RPT_MMUL) X+ { X+ if (regno & (VF_MASK_MR_RXC << VF_SH_MR_RXC)) X+ regno &= ~(VF_MASK_MR_RXC << VF_SH_MR_RXC); X+ else X+ regno |= (VF_MASK_MR_RXC << VF_SH_MR_RXC); X+ } X+ ip->insn_opcode |= (regno & VF_MASK_VS) << VF_SH_VS; X+ break; X+ case 't': X+ ip->insn_opcode |= (regno & VF_MASK_VT) << VF_SH_VT; X+ break; X+ case 'd': X+ case 'v': X+ case 'x': X+ ip->insn_opcode |= (regno & VF_MASK_VD) << VF_SH_VD; X+ break; X+ case 'm': X+ { X+ int vmregL = (regno >> 0) & VF_MASK_VML; X+ int vmregH = (regno >> 5) & VF_MASK_VMH; X+ ip->insn_opcode |= (vmregL << VF_SH_VML) X+ | (vmregH << VF_SH_VMH); X+ } X+ break; X+ case 'n': X+ { X+ int vmregL = (regno >> 0) & VF_MASK_VNL; X+ int vmregH = (regno >> 5) & VF_MASK_VNH; X+ ip->insn_opcode |= (vmregL << VF_SH_VNL) X+ | (vmregH << VF_SH_VNH); X+ } X+ break; X+ } X+ args++; X+ X+ /* now check for vfpu prefixes if necessary */ X+ if (*s == '[') X+ { X+ char *prefix_out = NULL; X+ bfd_boolean *prefix_bool = NULL; X+ char *prefix_type = NULL; X+ int num_args = 0; X+ char *ob = ++s; X+ bfd_boolean has_w = FALSE; X+ bfd_boolean has_z = FALSE; X+ bfd_boolean has_y = FALSE; X+ bfd_boolean has_operator = FALSE; X+ bfd_boolean has_saturater = FALSE; X+ X+ switch (*args) X+ { X+ case 'w': /* only swizzle */ X+ case 's': /* source prefix */ X+ prefix_bool = &vfpu_sprefix; X+ prefix_out = vfpu_sprefix_str; X+ prefix_type = "source"; X+ break; X+ case 't': /* target prefix */ X+ prefix_bool = &vfpu_tprefix; X+ prefix_out = vfpu_tprefix_str; X+ prefix_type = "target"; X+ break; X+ case 'm': /* only write mask */ X+ case 'd': /* destination prefix */ X+ prefix_bool = &vfpu_dprefix; X+ prefix_out = vfpu_dprefix_str; X+ prefix_type = "destination"; X+ break; X+ case 'y': /* inhibit */ X+ prefix_bool = NULL; X+ prefix_type = "source"; X+ break; X+ case 'x': /* inhibit */ X+ prefix_bool = NULL; X+ prefix_type = "target"; X+ break; X+ case 'z': /* inhibit */ X+ prefix_bool = NULL; X+ prefix_type = "destination"; X+ break; X+ } X+ X+ for ( ; *s != '\0' && *s != ']'; s++) X+ { X+ switch (*s) X+ { X+ case ',': X+ /* count no. of params for syntax check */ X+ num_args++; X+ break; X+ case ' ': X+ case '\t': X+ break; X+ case 'm': X+ case 'M': X+ case 'x': X+ case 'X': X+ break; X+ case 'y': X+ case 'Y': X+ has_y = TRUE; X+ break; X+ case 'z': X+ case 'Z': X+ has_z = TRUE; X+ break; X+ case 'w': X+ case 'W': X+ has_w = TRUE; X+ break; X+ default: X+ if (*args == 'w') X+ has_operator = TRUE; X+ if (*args == 'm') X+ has_saturater = TRUE; X+ } X+ } X+ X+ if (*s == ']') X+ { X+ if (prefix_bool) X+ { X+ *prefix_bool = TRUE; X+ strncpy (prefix_out, ob, s - ob); X+ prefix_out[s - ob] = '\0'; X+ s++; X+ } X+ else X+ { X+ as_bad (_("%s cannot use %s prefix"), X+ insn->name, prefix_type); X+ s++; X+ continue; X+ } X+ } X+ else X+ { X+ as_bad (_("parse error (%s)"), ob - 1); X+ return; X+ } X+ X+ if (num_args != regtype - '0') X+ { X+ as_bad (_("%s prefix specification requires %d parameters - [%s]"), X+ prefix_type, regtype - '0' + 1, X+ prefix_out); X+ } X+ else X+ { X+ int i = 8 - ((3 - num_args) * 2); X+ char dummy_d[] = " m,m,m,m"; X+ char dummy_st[] = " x,y,z,w"; X+ X+ if (*args == 'd' || *args == 'm') X+ { X+ strcat (prefix_out, dummy_d + i); X+ if (has_saturater) X+ { X+ as_bad (_("%s is restricted to mask destination prefixes only"), X+ insn->name); X+ } X+ } X+ else X+ { X+ strcat (prefix_out, dummy_st + i); X+ if (has_operator) X+ { X+ as_bad (_("%s is restricted to swizzle %s prefixes only"), X+ insn->name, prefix_type); X+ } X+ /* semantic check, w can't be specified for X+ s, p, or t instructions same goes for X+ z for p and s, and y for scalars */ X+ if ((has_y && num_args == 0) X+ || (has_z && num_args < 2) X+ || (has_w && num_args < 3)) X+ { X+ as_bad (_("%s swizzle operand is out of range in [%s]"), X+ prefix_type, prefix_out); X+ } X+ } X+ } X+ } X+ X+ continue; X+ } X+ break; X+ X+ case 'q': /* VFPU destination control register */ X+ case 'r': /* VFPU source control register */ X+ { X+ if ((s[0] == '$') && ISDIGIT (s[1])) X+ { X+ s++; X+ regno = 0; X+ do X+ { X+ regno *= 10; X+ regno += *s - '0'; X+ ++s; X+ } X+ while (ISDIGIT (*s)); X+ X+ if ((regno < VF_MIN_CR) || (regno > VF_MAX_CR)) X+ as_bad (_("Invalid VFPU control register number (%d)"), X+ regno); X+ X+ else if (!((regno >= VF_MIN_VCR) && (regno <= VF_MAX_VCR))) X+ as_bad (_("Improper VFPU control register number (%d)"), X+ regno); X+ X+ switch (*args) X+ { X+ case 'q': X+ ip->insn_opcode |= (regno & VF_MASK_VCD) << VF_SH_VCD; X+ break; X+ case 'r': X+ ip->insn_opcode |= (regno & VF_MASK_VCS) << VF_SH_VCS; X+ break; X+ } X+ } X+ else X+ { X+ as_bad (_("Invalid VFPU control register name (%s)"), s); X+ } X+ X+ continue; X+ } X+ break; X+ X+ case 'f': /* condition code */ X+ { X+ int cond = 0; X+ if (ISDIGIT (s[0])) X+ { X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ cond = imm_expr.X_add_number; X+ if ((cond < VF_MIN_CC) || (cond > VF_MAX_CC)) X+ as_bad (_("Invalid VFPU condition code (%d)"), cond); X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ } X+ else X+ { X+ static const char * const vfpu_cond_names[] = { X+ "FL", "EQ", "LT", "LE", X+ "TR", "NE", "GE", "GT", X+ "EZ", "EN", "EI", "ES", X+ "NZ", "NN", "NI", "NS" }; X+ for (cond = VF_MIN_CC; cond <= VF_MAX_CC; cond++) X+ { X+ if (strncasecmp(vfpu_cond_names[cond], s, 2) == 0) X+ break; X+ } X+ if ((cond < VF_MIN_CC) || (cond > VF_MAX_CC)) X+ as_bad (_("Invalid VFPU condition code (%s)"), s); X+ X+ s += 2; X+ } X+ X+ args++; X+ if ((cond == 0) || (cond == 4)) X+ { X+ } X+ else if (cond & 0x8) X+ { X+ if (*args - '0' < 1) X+ as_bad (_("Invalid VFPU condition oparetion")); X+ } X+ else X+ { X+ if (*args - '0' < 2) X+ as_bad (_("Invalid VFPU condition oparetion")); X+ } X+ X+ ip->insn_opcode |= (cond & VF_MASK_CC) << VF_SH_CC; X+ continue; X+ } X+ break; X+ X+ case 'a': /* constant code */ X+ { X+ int cst = 0; X+ if (ISDIGIT (s[0])) X+ { X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ cst = imm_expr.X_add_number; X+ if ((cst < VF_MIN_CONST) || (cst > VF_MAX_CONST)) X+ { X+ as_bad (_("Improper constant code (%d)"), cst); X+ cst &= VF_MASK_CONST; X+ } X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ } X+ else X+ { X+ static const char * const vfpu_const_names[] = { X+ "", "VFPU_HUGE", "VFPU_SQRT2", "VFPU_SQRT1_2", X+ "VFPU_2_SQRTPI", "VFPU_2_PI", "VFPU_1_PI", "VFPU_PI_4", X+ "VFPU_PI_2", "VFPU_PI", "VFPU_E", "VFPU_LOG2E", X+ "VFPU_LOG10E", "VFPU_LN2", "VFPU_LN10", "VFPU_2PI", X+ "VFPU_PI_6", "VFPU_LOG10TWO", "VFPU_LOG2TEN", X+ "VFPU_SQRT3_2"}; X+ for (cst = VF_MIN_CONST; cst <= VF_MAX_CONST; cst++) X+ { X+ if (strcasecmp(vfpu_const_names[cst], s) == 0) X+ break; X+ } X+ if ((cst < VF_MIN_CONST) || (cst > VF_MAX_CONST)) X+ as_bad (_("Invalid constant code (%s)"), s); X+ else X+ s += strlen(vfpu_const_names[cst]); X+ } X+ X+ ip->insn_opcode |= cst << VF_SH_CONST; X+ } X+ continue; X+ X+ case 'b': /* scale exponent */ X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ if ((unsigned long) imm_expr.X_add_number > VF_MAX_SCALE) X+ { X+ as_bad (_("Improper scale (%lu)"), X+ (unsigned long) imm_expr.X_add_number); X+ imm_expr.X_add_number &= VF_MASK_SCALE; X+ } X+ ip->insn_opcode |= imm_expr.X_add_number << VF_SH_SCALE; X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ continue; X+ X+ case 'c': /* branch condition code bit */ X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ if ((unsigned long) imm_expr.X_add_number > VF_MAX_BCOND) X+ { X+ as_bad (_("Improper condition bit (%lu)"), X+ (unsigned long) imm_expr.X_add_number); X+ imm_expr.X_add_number &= VF_MASK_BCOND; X+ } X+ ip->insn_opcode |= imm_expr.X_add_number << VF_SH_BCOND; X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ continue; X+ X+ case 'e': /* move condition code bit */ X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ if ((unsigned long) imm_expr.X_add_number > VF_MAX_MCOND) X+ { X+ as_bad (_("Improper condition bit (%lu)"), X+ (unsigned long) imm_expr.X_add_number); X+ imm_expr.X_add_number &= VF_MASK_MCOND; X+ } X+ ip->insn_opcode |= imm_expr.X_add_number << VF_SH_MCOND; X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ continue; X+ X+ case 'i': /* wrap exponent */ X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ if ((unsigned long) imm_expr.X_add_number > VF_MAX_WRAP) X+ { X+ as_bad (_("Improper wrap (%lu)"), X+ (unsigned long) imm_expr.X_add_number); X+ imm_expr.X_add_number &= VF_MASK_WRAP; X+ } X+ ip->insn_opcode |= imm_expr.X_add_number << VF_SH_WRAP; X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ continue; X+ X+ case 'w': /* rotation code */ X+ if (s[0] == '[') X+ { X+ char *rot_str = s; X+ int rot_idx = 0; X+ int rot_neg = 0; X+ int rot_sin = 3; X+ int rot_cos = 3; X+ int rot_err = 0; X+ int rot_n; X+ int rot_neg_n = 0; X+ int rot_sin_n = 0; X+ int rot_cos_n = 0; X+ int rot_code; X+ X+ if ((ip->insn_opcode & VFPU_MASK_DTYPE) == VFPU_PAIR) X+ rot_n = 2; X+ else if ((ip->insn_opcode & VFPU_MASK_DTYPE) == VFPU_TRIPLE) X+ rot_n = 3; X+ else if ((ip->insn_opcode & VFPU_MASK_DTYPE) == VFPU_QUAD) X+ rot_n = 4; X+ else X+ rot_n = 0; X+ X+ s++; X+ while ((s[0] != ']') && (s[0] != '\0')) X+ { X+ if (s[0] == '-') X+ { X+ if ((s[1] != 's') && (s[1] != 'S')) X+ { X+ rot_err = 1; X+ break; X+ } X+ rot_neg = 1; X+ rot_neg_n++; X+ s++; X+ } X+ X+ if (s[0] == ',') X+ rot_idx++; X+ else if ((s[0] == 'c') || (s[0] == 'C')) X+ { X+ rot_cos = rot_idx; X+ rot_cos_n++; X+ } X+ else if ((s[0] == 's') || (s[0] == 'S')) X+ { X+ rot_sin = rot_idx; X+ rot_sin_n++; X+ } X+ else if (ISSPACE(s[0]) || (s[0] == '0')) X+ ; X+ else X+ { X+ rot_err = 1; X+ break; X+ } X+ X+ s++; X+ } X+ X+ if (s[0] == ']') X+ rot_idx++; X+ else X+ rot_err = 1; X+ s++; X+ X+ if ((rot_sin_n == 0) && (rot_cos_n == 0)) X+ { X+ if (rot_n == 2) X+ rot_sin = 2; X+ else if ((rot_n == 4) || (rot_n == 3)) X+ rot_err = 1; X+ } X+ X+ if (rot_cos_n > 1) X+ rot_err = 1; X+ X+ if (rot_sin_n > 1) X+ { X+ if (((rot_sin_n + rot_cos_n) != rot_n) X+ || ((rot_n == 4) && (rot_cos_n == 0))) X+ rot_err = 1; X+ } X+ X+ if (rot_neg && (rot_neg_n != rot_sin_n)) X+ rot_err = 1; X+ X+ if (rot_sin_n > 1) X+ rot_sin = rot_cos; X+ X+ if (rot_err || (rot_n != rot_idx)) X+ as_bad (_("Invalid rotation code (%s)"), rot_str); X+ X+ rot_code = ((rot_neg & VF_MASK_ROT_NEG) << VF_SH_ROT_NEG) X+ | ((rot_cos & VF_MASK_ROT_COS) << VF_SH_ROT_COS) X+ | ((rot_sin & VF_MASK_ROT_SIN) << VF_SH_ROT_SIN); X+ ip->insn_opcode |= rot_code << VF_SH_ROT; X+ } X+ else X+ { X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ if ((unsigned long) imm_expr.X_add_number > VF_MAX_ROT) X+ { X+ as_bad (_("Improper rotation code (%lu)"), X+ (unsigned long) imm_expr.X_add_number); X+ imm_expr.X_add_number &= VF_MASK_ROT; X+ } X+ ip->insn_opcode |= imm_expr.X_add_number << VF_SH_ROT; X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ } X+ continue; X+ X+ case 'u': /* half float */ X+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) X+ { X+ my_getExpression (&imm_expr, s); X+ check_absolute_expr (ip, &imm_expr); X+ if ((unsigned long) imm_expr.X_add_number > VF_MAX_HFLOAT) X+ { X+ as_bad (_("Improper half floating point constant: (%lu)"), X+ (unsigned long) imm_expr.X_add_number); X+ imm_expr.X_add_number &= VF_MASK_HFLOAT; X+ } X+ ip->insn_opcode |= imm_expr.X_add_number << VF_SH_HFLOAT; X+ imm_expr.X_op = O_absent; X+ s = expr_end; X+ continue; X+ } X+ else X+ { X+ char *save_in; X+ char *err; X+ int len; X+ unsigned int length; X+ unsigned char temp[8]; X+ unsigned int f32, f16; X+ int exponent32, exponent16; X+ int fraction32, fraction16; X+ int sign; X+ char f16_str[8]; X+ X+ save_in = input_line_pointer; X+ input_line_pointer = s; X+ err = md_atof ('f', (char *) temp, &len); X+ length = len; X+ s = input_line_pointer; X+ input_line_pointer = save_in; X+ if (err != NULL && *err != '\0') X+ { X+ as_bad (_("Bad half floating point constant: %s"), err); X+ memset (temp, '\0', sizeof temp); X+ length = 4; X+ } X+ X+ if (! target_big_endian) X+ f32 = bfd_getl32 (temp); X+ else X+ f32 = bfd_getb32 (temp); X+ X+ sign = (f32 >> VF_SH_F32_SIGN) & VF_MASK_F32_SIGN; X+ exponent32 = (f32 >> VF_SH_F32_EXP) & VF_MASK_F32_EXP; X+ fraction32 = (f32 >> VF_SH_F32_FRA) & VF_MASK_F32_FRA; X+ exponent16 = exponent32 X+ - VF_BIAS_F32_EXP + VF_BIAS_F16_EXP; X+ X+ if (exponent16 < VF_MIN_F16_EXP) X+ { X+ if ((exponent32 == VF_MIN_F32_EXP) X+ && (fraction32 == 0)) X+ { // zero X+ exponent16 = VF_MIN_F16_EXP; X+ fraction16 = 0; X+ } X+ else X+ { // underflow X+ float* p; X+ p = (float*) &f32; X+ as_warn (_("Half floating point underflow: %g"), X+ *p); X+ exponent16 = VF_MIN_F16_EXP; X+ fraction16 = 0; X+ } X+ } X+ else if (exponent16 > VF_MAX_F16_EXP) X+ { X+ if (exponent32 != VF_MAX_F32_EXP) X+ { // overflow X+ as_warn (_("Half floating point overflow: %g"), X+ *(float *)&f32); X+ exponent16 = VF_MAX_F16_EXP; X+ fraction16 = 0; X+ } X+ else X+ { X+ if (fraction32 == 0) X+ { // infinity X+ exponent16 = VF_MAX_F16_EXP; X+ fraction16 = 0; X+ } X+ else X+ { // NaN X+ exponent16 = VF_MAX_F16_EXP; X+ fraction16 = 1; X+ } X+ } X+ } X+ else X+ { X+ fraction16 = (f32 >> (VF_SH_F32_EXP - VF_SH_F16_EXP)) X+ & VF_MASK_F16_FRA; X+ } X+ X+ f16 = (sign << VF_SH_F16_SIGN) X+ | (exponent16 << VF_SH_F16_EXP) X+ | (fraction16 << VF_SH_F16_FRA); X+ ip->insn_opcode |= (f16 & VF_MASK_HFLOAT) << VF_SH_HFLOAT; X+ X+ sprintf(f16_str, "0x%04x", f16); X+ my_getExpression (&imm_expr, f16_str); X+ X+ continue; X+ } X+ break; X+ X+ case 'z': /* read/write access code */ X+ { X+ int rwb = 0; X+ X+ if (strncasecmp (s, "WT", 2) == 0) X+ rwb = 0x0; X+ else if (strncasecmp (s, "WB", 2) == 0) X+ rwb = 0x1; X+ else X+ as_bad (_("Invalid memory access type (%s)"), s); X+ X+ s += 2; X+ ip->insn_opcode |= (rwb & VF_MASK_RWB) << VF_SH_RWB; X+ X+ continue; X+ } X+ X+ case '0': /* source or target prefix code (X) */ X+ case '1': /* source or target prefix code (Y) */ X+ case '2': /* source or target prefix code (Z) */ X+ case '3': /* source or target prefix code (W) */ X+ { X+ int operand; X+ int shift; X+ X+ int pfx_neg = 0; X+ int pfx_cst = 0; X+ int pfx_abs = 0; X+ int pfx_swz = 0; X+ int pfx_err = 0; X+ int cst = 0; X+ char *pfx_str = s; X+ X+ if (s[0] == '-') X+ { // sign code X+ pfx_neg = 1; X+ s++; X+ } X+ X+ if (ISDIGIT (s[0])) X+ { // constant X+ pfx_cst = 1; X+ X+ if (s[0] == '0') X+ cst = 0; X+ else if (s[0] == '1') X+ { X+ if (s[1] == '/') X+ { X+ s += 2; X+ if (s[0] == '2') X+ cst = 3; X+ else if (s[0] == '3') X+ cst = 5; X+ else if (s[0] == '4') X+ cst = 6; X+ else if (s[0] == '6') X+ cst = 7; X+ else X+ pfx_err = 1; X+ } X+ else X+ { X+ cst = 1; X+ } X+ } X+ else if (s[0] == '2') X+ cst = 2; X+ else if (s[0] == '3') X+ cst = 4; X+ else X+ pfx_err = 1; X+ X+ pfx_abs = (cst >> 2) & 0x1; X+ pfx_swz = (cst >> 0) & 0x3; X+ s++; X+ } X+ else X+ { // variable X+ X+ if (s[0] == '|') X+ { // abs X+ pfx_abs = 1; X+ s++; X+ } X+ X+ if ((s[0] == 'X') || (s[0] == 'x')) X+ { X+ pfx_swz = 0; X+ s++; X+ } X+ else if ((s[0] == 'Y') || (s[0] == 'y')) X+ { X+ pfx_swz = 1; X+ s++; X+ } X+ else if ((s[0] == 'Z') || (s[0] == 'z')) X+ { X+ pfx_swz = 2; X+ s++; X+ } X+ else if ((s[0] == 'W') || (s[0] == 'w')) X+ { X+ pfx_swz = 3; X+ s++; X+ } X+ else if ((s[0] == ',') || IS_SPACE_OR_NUL (s[0]) X+ || (s[0] == '|')) X+ { X+ pfx_swz = *args - '0'; X+ } X+ else X+ pfx_err = 1; X+ X+ if (pfx_err == 0) X+ { X+ if (s[0] == '|') X+ { X+ s++; X+ if (pfx_abs == 0) X+ pfx_err = 1; X+ } X+ else X+ { X+ if (pfx_abs == 1) X+ pfx_err = 1; X+ } X+ } X+ } X+ X+ if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0]))) X+ pfx_err = 1; X+ X+ if (pfx_err) X+ as_bad (_("Invalid prefix format (%s)"), pfx_str); X+ X+ shift = *args - '0'; X+ X+ operand = (pfx_neg << (VF_SH_PFX_NEG + shift)) X+ | (pfx_cst << (VF_SH_PFX_CST + shift)) X+ | (pfx_abs << (VF_SH_PFX_ABS + shift)) X+ | (pfx_swz << (VF_SH_PFX_SWZ + shift * 2)); X+ X+ ip->insn_opcode |= operand; X+ continue; X+ } X+ X+ case '4': /* destination prefix code (X) */ X+ case '5': /* destination prefix code (Y) */ X+ case '6': /* destination prefix code (Z) */ X+ case '7': /* destination prefix code (W) */ X+ { X+ int operand; X+ int shift; X+ static const char order[] = "xyzwXYZW"; X+ X+ int pfx_msk = 0; X+ int pfx_sat = 0; X+ char *pfx_str = s; X+ X+ if (s[0] == '[') X+ s++; X+ if (s[0] == '-') /* -1:1, skip the minus symbol */ X+ s++; X+ X+ if ((s[0] == 'm') || (s[0] == 'M')) X+ { X+ pfx_msk = 1; X+ s++; X+ } X+ else if (s[0] == '0') /* 0:1 */ X+ { X+ pfx_sat = 1; X+ s++; X+ } X+ else if (s[0] == '1') /* -1:1 or -1:+1 */ X+ { X+ pfx_sat = 3; X+ s++; X+ } X+ else if ((s[0] == order[(*args) - '4']) X+ || (s[0] == order[(*args) - '4' + 4])) X+ { X+ pfx_sat = 0; X+ s++; X+ } X+ X+ if (s[0] == ':') /* skip the :1 or :+1 part of the expression */ X+ { X+ s++; X+ if (s[0] == '+') X+ s++; X+ if (s[0] == '1') X+ s++; X+ } X+ if (s[0] == ']') X+ s++; X+ X+ if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0]))) X+ as_bad (_("Invalid prefix format (%s)"), pfx_str); X+ X+ shift = *args - '4'; X+ operand = (pfx_msk << (VF_SH_PFX_MSK + shift)) X+ | (pfx_sat << (VF_SH_PFX_SAT + shift * 2)); X+ X+ ip->insn_opcode |= operand; X+ continue; X+ } X+ } X+ break; X+ X+ case 'b': /* base register */ X+ case 'd': /* destination register */ X+ case 's': /* source register */ X+ case 't': /* target register */ X+ case 'r': /* both target and source */ X+ case 'v': /* both dest and source */ X+ case 'w': /* both dest and target */ X+ case 'E': /* coprocessor target register */ X+ case 'G': /* coprocessor destination register */ X+ case 'K': /* 'rdhwr' destination register */ X+ case 'x': /* ignore register name */ X+ case 'z': /* must be zero register */ X+ case 'U': /* destination register (clo/clz). */ X+ s_reset = s; X+ if (s[0] == '$') X+ { X+ X+ if (ISDIGIT (s[1])) X+ { X+ ++s; X regno = 0; X do X { X@@ -8273,30 +9967,27 @@ X goto notreg; X else X { X- if (s[1] == 'r' && s[2] == 'a') X+ const char regName[32][5] = X { X- s += 3; X- regno = RA; X- } X- else if (s[1] == 'f' && s[2] == 'p') X+ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", X+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", X+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", X+ "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" X+ }; X+ int i; X+ X+ for(i = 0; i < 32; i++) X { X- s += 3; X- regno = FP; X- } X- else if (s[1] == 's' && s[2] == 'p') X+ if(strncmp(&s[1], regName[i], strlen(regName[i])) == 0) X { X- s += 3; X- regno = SP; X+ break; X } X- else if (s[1] == 'g' && s[2] == 'p') X- { X- s += 3; X- regno = GP; X } X- else if (s[1] == 'a' && s[2] == 't') X+ X+ if(i < 32) X { X- s += 3; X- regno = AT; X+ s += strlen(regName[i]) + 1; X+ regno = i; X } X else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') X { X@@ -8485,6 +10176,7 @@ X X if ((regno & 1) != 0 X && HAVE_32BIT_FPRS X+ && ! CPU_IS_ALLEGREX (mips_opts.arch) X && ! (strcmp (str, "mtc1") == 0 X || strcmp (str, "mfc1") == 0 X || strcmp (str, "lwc1") == 0 X@@ -13743,6 +15435,8 @@ X X /* MIPS II */ X { "r6000", 0, ISA_MIPS2, CPU_R6000 }, X+ /* Sony PSP "Allegrex" CPU core */ X+ { "allegrex", 0, ISA_MIPS2, CPU_ALLEGREX }, X X /* MIPS III */ X { "r4000", 0, ISA_MIPS3, CPU_R4000 }, END-of-psptoolchain-binutils/files/patch-gas-config-tc-mips.c echo x - psptoolchain-binutils/files/patch-gas-configure.in sed 's/^X//' >psptoolchain-binutils/files/patch-gas-configure.in << 'END-of-psptoolchain-binutils/files/patch-gas-configure.in' X--- gas/configure.in.orig 2005-03-01 00:43:57.000000000 +0000 X+++ gas/configure.in 2006-05-09 02:55:36.000000000 +0100 X@@ -222,6 +222,9 @@ X mips64vr | mips64vrel) X mips_cpu=vr4100 X ;; X+ mipsallegrex | mipsallegrexel) X+ mips_cpu=allegrex X+ ;; X mipsisa32r2* | mipsisa64r2*) X changequote(,)dnl X mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` END-of-psptoolchain-binutils/files/patch-gas-configure.in echo x - psptoolchain-binutils/files/patch-gas-testsuite-gas-mips-mips.exp sed 's/^X//' >psptoolchain-binutils/files/patch-gas-testsuite-gas-mips-mips.exp << 'END-of-psptoolchain-binutils/files/patch-gas-testsuite-gas-mips-mips.exp' X--- gas/testsuite/gas/mips/mips.exp.orig 2005-04-19 18:09:45.000000000 +0100 X+++ gas/testsuite/gas/mips/mips.exp 2006-05-09 02:55:36.000000000 +0100 X@@ -382,6 +382,9 @@ X mips_arch_create sb1 64 mips64 { mips3d } \ X { -march=sb1 -mtune=sb1 } { -mmips:sb1 } \ X { mipsisa64sb1-*-* mipsisa64sb1el-*-* } X+mips_arch_create allegrex 32 mips2 { ror } \ X+ { -march=allegrex -mtune=allegrex } { -mmips:allegrex } \ X+ { mipsallegrex-*-* mipsallegrexel-*-* } X X X # END-of-psptoolchain-binutils/files/patch-gas-testsuite-gas-mips-mips.exp echo x - psptoolchain-binutils/files/patch-include-elf-common.h sed 's/^X//' >psptoolchain-binutils/files/patch-include-elf-common.h << 'END-of-psptoolchain-binutils/files/patch-include-elf-common.h' X--- include/elf/common.h.orig 2004-10-08 14:55:08.000000000 +0100 X+++ include/elf/common.h 2006-05-09 02:55:36.000000000 +0100 X@@ -93,6 +93,7 @@ X #define ET_HIOS 0xFEFF /* Operating system-specific */ X #define ET_LOPROC 0xFF00 /* Processor-specific */ X #define ET_HIPROC 0xFFFF /* Processor-specific */ X+#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */ X X /* Values for e_machine, which identifies the architecture. These numbers X are officially assigned by registry@caldera.com. See below for a list of END-of-psptoolchain-binutils/files/patch-include-elf-common.h echo x - psptoolchain-binutils/files/patch-include-opcode-mips.h sed 's/^X//' >psptoolchain-binutils/files/patch-include-opcode-mips.h << 'END-of-psptoolchain-binutils/files/patch-include-opcode-mips.h' X--- include/opcode/mips.h.orig 2005-03-03 11:58:10.000000000 +0000 X+++ include/opcode/mips.h 2006-05-09 02:55:36.000000000 +0100 X@@ -171,6 +171,228 @@ X #define MDMX_FMTSEL_VEC_QH 0x15 X #define MDMX_FMTSEL_VEC_OB 0x16 X X+#include "vfpu.h" X+ X+#define VF_MASK_VT 0x7f X+#define VF_SH_VT 16 X+#define VF_MASK_VS 0x7f X+#define VF_SH_VS 8 X+#define VF_MASK_VD 0x7f X+#define VF_SH_VD 0 X+#define VF_MASK_VML 0x1f X+#define VF_SH_VML 16 X+#define VF_MASK_VMH 0x3 X+#define VF_SH_VMH 0 X+#define VF_MASK_VNL 0x1f X+#define VF_SH_VNL 16 X+#define VF_MASK_VNH 0x1 X+#define VF_SH_VNH 0 X+#define VF_MASK_OFFSET 0x3fff X+#define VF_SH_OFFSET 2 X+#define VF_MASK_CC 0xf X+#define VF_SH_CC 0 X+#define VF_MASK_CONST 0x1f X+#define VF_SH_CONST 16 X+#define VF_MASK_SCALE 0x1f X+#define VF_SH_SCALE 16 X+#define VF_MASK_BCOND 0x7 X+#define VF_SH_BCOND 18 X+#define VF_MASK_MCOND 0x7 X+#define VF_SH_MCOND 16 X+#define VF_MASK_VCD 0xff X+#define VF_SH_VCD 0 X+#define VF_MASK_VCS 0xff X+#define VF_SH_VCS 8 X+#define VF_MASK_ROT 0x1f X+#define VF_SH_ROT 16 X+#define VF_MASK_WRAP 0xff X+#define VF_SH_WRAP 16 X+#define VF_MASK_TSIGN 0x1 X+#define VF_SH_TSIGN 5 X+#define VF_MASK_BMCOND 0x1f X+#define VF_SH_BMCOND 0 X+#define VF_MASK_HFLOAT 0xffff X+#define VF_SH_HFLOAT 0 X+#define VF_MASK_PFX 0xffffff X+#define VF_SH_PFX 0 X+#define VF_MASK_RWB 0x1 X+#define VF_SH_RWB 1 X+ X+#define VF_MASK_PFX_SWZ 0x3 X+#define VF_SH_PFX_SWZ 0 X+#define VF_MASK_PFX_ABS 0x1 X+#define VF_SH_PFX_ABS 8 X+#define VF_MASK_PFX_CST 0x1 X+#define VF_SH_PFX_CST 12 X+#define VF_MASK_PFX_NEG 0x1 X+#define VF_SH_PFX_NEG 16 X+#define VF_MASK_PFX_SAT 0x3 X+#define VF_SH_PFX_SAT 0 X+#define VF_MASK_PFX_MSK 0x1 X+#define VF_SH_PFX_MSK 8 X+ X+#define VF_MASK_ROT_COS 0x3 X+#define VF_SH_ROT_COS 0 X+#define VF_MASK_ROT_SIN 0x3 X+#define VF_SH_ROT_SIN 2 X+#define VF_MASK_ROT_NEG 0x1 X+#define VF_SH_ROT_NEG 4 X+ X+#define VF_MASK_MR_MTX 0x7 X+#define VF_SH_MR_MTX 2 X+#define VF_MASK_MR_IDX 0x3 X+#define VF_SH_MR_IDX 0 X+#define VF_MASK_MR_FSL 0x3 X+#define VF_SH_MR_FSL 5 X+#define VF_MASK_MR_RXC 0x1 X+#define VF_SH_MR_RXC 5 X+#define VF_MASK_MR_VFSL 0x1 X+#define VF_SH_MR_VFSL 6 X+ X+#define VF_MAX_MR_MTX 7 X+#define VF_MAX_MR_IDX 3 X+#define VF_MAX_MR_FSL 3 X+#define VF_MAX_MR_VIDX 1 X+#define VF_MAX_MR_VFSL 1 X+ X+#define VF_MIN_MR 0 X+#define VF_MAX_MR 127 X+#define VF_MIN_CR 128 X+#define VF_MAX_CR 255 X+#define VF_MIN_VCR 128 X+#define VF_MAX_VCR 143 X+#define VF_MIN_CC 0 X+#define VF_MAX_CC 15 X+#define VF_MIN_CONST 1 X+#define VF_MAX_CONST 19 X+#define VF_MIN_SCALE 0 X+#define VF_MAX_SCALE 31 X+#define VF_MIN_BCOND 0 X+#define VF_MAX_BCOND 5 X+#define VF_MIN_MCOND 0 X+#define VF_MAX_MCOND 6 X+#define VF_MIN_WRAP 0 X+#define VF_MAX_WRAP 255 X+#define VF_MIN_ROT 0 X+#define VF_MAX_ROT 31 X+#define VF_MIN_TSIGN 0 X+#define VF_MAX_TSIGN 1 X+#define VF_MIN_BMCOND 0 X+#define VF_MAX_BMCOND 31 X+#define VF_MIN_HFLOAT 0 X+#define VF_MAX_HFLOAT 0xffff X+ X+#define VF_MASK_F32_SIGN 0x1 X+#define VF_SH_F32_SIGN 31 X+#define VF_MASK_F32_EXP 0xff X+#define VF_SH_F32_EXP 23 X+#define VF_MASK_F32_FRA 0x7fffff X+#define VF_SH_F32_FRA 0 X+#define VF_MASK_F16_SIGN 0x1 X+#define VF_SH_F16_SIGN 15 X+#define VF_MASK_F16_EXP 0x1f X+#define VF_SH_F16_EXP 10 X+#define VF_MASK_F16_FRA 0x3ff X+#define VF_SH_F16_FRA 0 X+ X+#define VF_MIN_F32_EXP 0 X+#define VF_MAX_F32_EXP 255 X+#define VF_BIAS_F32_EXP 127 X+#define VF_MIN_F16_EXP 0 X+#define VF_MAX_F16_EXP 31 X+#define VF_BIAS_F16_EXP 15 X+ X+#define OP_SH_VFPU_DELTA 0 X+#define OP_MASK_VFPU_DELTA 0xfffc X+#define OP_SH_VFPU_IMM3 16 X+#define OP_MASK_VFPU_IMM3 0x7 X+#define OP_SH_VFPU_IMM5 16 X+#define OP_MASK_VFPU_IMM5 0x1f X+#define OP_SH_VFPU_IMM8 16 X+#define OP_MASK_VFPU_IMM8 0xff X+#define OP_SH_VFPU_CC 18 /* Condition code. */ X+#define OP_MASK_VFPU_CC 0x7 X+#define OP_SH_VFPU_CONST 16 X+#define OP_MASK_VFPU_CONST 0x1f X+#define OP_SH_VFPU_COND 0 /* Conditional compare. */ X+#define OP_MASK_VFPU_COND 0xf X+#define OP_SH_VFPU_VMTVC 0 X+#define OP_MASK_VFPU_VMTVC 0xff X+#define OP_SH_VFPU_VMFVC 8 X+#define OP_MASK_VFPU_VMFVC 0xff X+#define OP_SH_VFPU_RWB 1 X+#define OP_MASK_VFPU_RWB 0x1 X+#define OP_SH_VFPU_ROT 16 /* Rotators used in vrot. */ X+#define OP_MASK_VFPU_ROT 0x1f X+#define OP_SH_VFPU_FLOAT16 0 X+#define OP_MASK_VFPU_FLOAT16 0xffff X+ X+/* VFPU registers. */ X+#define OP_SH_VFPU_VD 0 X+#define OP_MASK_VFPU_VD 0x7f X+#define OP_SH_VFPU_VS 8 X+#define OP_MASK_VFPU_VS 0x7f X+#define OP_SH_VFPU_VT 16 X+#define OP_MASK_VFPU_VT 0x7f X+#define OP_SH_VFPU_VT_LO 16 /* Bits 0-4 of vt. */ X+#define OP_MASK_VFPU_VT_LO 0x1f X+#define OP_SH_VFPU_VT_HI 5 /* Right-shifted. */ X+#define OP_MASK_VFPU_VT_HI1 0x1 /* Bit 5 of vt. */ X+#define OP_MASK_VFPU_VT_HI2 0x3 /* Bits 5-6 of vt. */ X+/* Special handling of vs in vmmul instructions. */ X+#define VFPU_OP_VT_VS_VD 0xff800000 X+#define VFPU_OPCODE_VMMUL 0xf0000000 X+ X+/* VFPU condition codes. FL and TR accept no arguments, while any conditions X+ above and including EZ only accept one argument. The rest require two X+ arguments. */ X+enum X+{ X+ VFPU_COND_FL, VFPU_COND_EQ, VFPU_COND_LT, VFPU_COND_LE, X+ VFPU_COND_TR, VFPU_COND_NE, VFPU_COND_GE, VFPU_COND_GT, X+ VFPU_COND_EZ, VFPU_COND_EN, VFPU_COND_EI, VFPU_COND_ES, X+ VFPU_COND_NZ, VFPU_COND_NN, VFPU_COND_NI, VFPU_COND_NS, X+ VFPU_NUM_CONDS X+}; X+ X+/* VFPU prefix instruction operands. The *_SH_* values really specify where X+ the bitfield begins, as VFPU prefix instructions have four operands X+ encoded within the immediate field. */ X+#define VFPU_SH_PFX_NEG 16 X+#define VFPU_MASK_PFX_NEG 0x1 /* Negation. */ X+#define VFPU_SH_PFX_CST 12 X+#define VFPU_MASK_PFX_CST 0x1 /* Constant. */ X+#define VFPU_SH_PFX_ABS_CSTHI 8 X+#define VFPU_MASK_PFX_ABS_CSTHI 0x1 /* Abs/Constant (bit 2). */ X+#define VFPU_SH_PFX_SWZ_CSTLO 0 X+#define VFPU_MASK_PFX_SWZ_CSTLO 0x3 /* Swizzle/Constant (bits 0-1). */ X+#define VFPU_SH_PFX_MASK 8 X+#define VFPU_MASK_PFX_MASK 0x1 /* Mask. */ X+#define VFPU_SH_PFX_SAT 0 X+#define VFPU_MASK_PFX_SAT 0x3 /* Saturation. */ X+ X+/* Special handling of the vrot instructions. */ X+#define VFPU_MASK_OP_SIZE 0x8080 /* Masks the operand size (pair, triple, quad). */ X+#define VFPU_OP_SIZE_PAIR 0x80 X+#define VFPU_OP_SIZE_TRIPLE 0x8000 X+#define VFPU_OP_SIZE_QUAD 0x8080 X+/* Note that these are within the rotators field, and not the full opcode. */ X+#define VFPU_SH_ROT_HI 2 X+#define VFPU_MASK_ROT_HI 0x3 X+#define VFPU_SH_ROT_LO 0 X+#define VFPU_MASK_ROT_LO 0x3 X+#define VFPU_SH_ROT_NEG 4 /* Negation. */ X+#define VFPU_MASK_ROT_NEG 0x1 X+ X+/* VFPU 16-bit floating-point format. */ X+#define VFPU_FLOAT16_EXP_MAX 0x1f X+#define VFPU_SH_FLOAT16_SIGN 15 X+#define VFPU_MASK_FLOAT16_SIGN 0x1 X+#define VFPU_SH_FLOAT16_EXP 10 X+#define VFPU_MASK_FLOAT16_EXP 0x1f X+#define VFPU_SH_FLOAT16_FRAC 0 X+#define VFPU_MASK_FLOAT16_FRAC 0x3ff X+ X /* This structure holds information for a particular instruction. */ X X struct mips_opcode X@@ -258,6 +480,29 @@ X Requires that "+A" or "+E" occur first to set position. X Enforces: 32 < (pos+size) <= 64. X X+ Sony Allegrex VFPU instructions: X+ "?o" X+ "?0" - "?3" X+ "?4" - "?7" X+ "?a" X+ "?b" X+ "?c" X+ "?e" X+ "?f" X+ "?i" X+ "?q" X+ "?r" X+ "?u" X+ "?w" X+ "?d" X+ "?m" X+ "?n" X+ "?s" X+ "?t" X+ "?v" X+ "?x" X+ "?z" X+ X Floating point instructions: X "D" 5 bit destination register (OP_*_FD) X "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) X@@ -442,6 +687,8 @@ X #define INSN_5400 0x01000000 X /* NEC VR5500 instruction. */ X #define INSN_5500 0x02000000 X+/* Sony Allegrex instruction. */ X+#define INSN_ALLEGREX 0x10000000 X X /* MIPS ISA defines, use instead of hardcoding ISA level. */ X X@@ -489,6 +736,7 @@ X #define CPU_MIPS64 64 X #define CPU_MIPS64R2 65 X #define CPU_SB1 12310201 /* octal 'SB', 01. */ X+#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */ X X /* Test for membership in an ISA including chip specific ISAs. INSN X is pointer to an element of the opcode table; ISA is the specified X@@ -510,6 +758,7 @@ X || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ X || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ X || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ X+ || (cpu == CPU_ALLEGREX && ((insn)->membership & INSN_ALLEGREX) != 0) \ X || 0) /* Please keep this term for easier source merging. */ X X /* This is a list of macro expanded instructions. X@@ -622,9 +871,25 @@ X M_LI_DD, X M_LI_S, X M_LI_SS, X+ M_LVHI_S_SS, X+ M_LVHI_P_SS, X+ M_LVI_S_SS, X+ M_LVI_P_SS, X+ M_LVI_T_SS, X+ M_LVI_Q_SS, X M_LL_AB, X M_LLD_AB, X M_LS_A, X+ M_LVHI_P, X+ M_LVHI_S, X+ M_LVI_P, X+ M_LVI_Q, X+ M_LVI_S, X+ M_LVI_T, X+ M_LVL_Q_AB, X+ M_LVR_Q_AB, X+ M_LV_Q_AB, X+ M_LV_Q_AB_2, X M_LW_A, X M_LW_AB, X M_LWC0_A, X@@ -635,6 +900,7 @@ X M_LWC2_AB, X M_LWC3_A, X M_LWC3_AB, X+ M_LV_S_AB, X M_LWL_A, X M_LWL_AB, X M_LWR_A, X@@ -714,6 +980,10 @@ X M_SUB_I, X M_SUBU_I, X M_SUBU_I_2, X+ M_SVL_Q_AB, X+ M_SV_Q_AB, X+ M_SVR_Q_AB, X+ M_SV_S_AB, X M_TEQ_I, X M_TGE_I, X M_TGEU_I, X@@ -728,14 +998,24 @@ X M_ULH_A, X M_ULHU, X M_ULHU_A, X+ M_ULV_Q, X+ M_ULV_Q_AB, X+ M_ULV_S, X M_ULW, X M_ULW_A, X M_USH, X M_USH_A, X+ M_USV_Q, X+ M_USV_Q_AB, X+ M_USV_S, X M_USW, X M_USW_A, X M_USD, X M_USD_A, X+ M_VCMOV_P, X+ M_VCMOV_Q, X+ M_VCMOV_S, X+ M_VCMOV_T, X M_XOR_I, X M_COP0, X M_COP1, END-of-psptoolchain-binutils/files/patch-include-opcode-mips.h echo x - psptoolchain-binutils/files/patch-ld-configure.tgt sed 's/^X//' >psptoolchain-binutils/files/patch-ld-configure.tgt << 'END-of-psptoolchain-binutils/files/patch-ld-configure.tgt' X--- ld/configure.tgt.orig 2005-02-08 19:54:27.000000000 +0000 X+++ ld/configure.tgt 2006-05-09 02:55:36.000000000 +0100 X@@ -428,6 +428,8 @@ X mips*vr4100-*-elf*) targ_emul=elf32b4300 ;; X mips*vr5000el-*-elf*) targ_emul=elf32l4300 ;; X mips*vr5000-*-elf*) targ_emul=elf32b4300 ;; X+mips*allegrexel-psp-elf*) targ_emul=elf_mipsallegrexel_psp X+ targ_extra_emuls="elf32elmip" ;; X mips*el-*-elf*) targ_emul=elf32elmip ;; X mips*-*-elf*) targ_emul=elf32ebmip ;; X mips*el-*-rtems*) targ_emul=elf32elmip ;; END-of-psptoolchain-binutils/files/patch-ld-configure.tgt echo x - psptoolchain-binutils/files/patch-ld-emulparams-elf_mipsallegrexel_psp.sh sed 's/^X//' >psptoolchain-binutils/files/patch-ld-emulparams-elf_mipsallegrexel_psp.sh << 'END-of-psptoolchain-binutils/files/patch-ld-emulparams-elf_mipsallegrexel_psp.sh' X--- ld/emulparams/elf_mipsallegrexel_psp.sh.orig 1970-01-01 01:00:00.000000000 +0100 X+++ ld/emulparams/elf_mipsallegrexel_psp.sh 2006-05-09 02:55:36.000000000 +0100 X@@ -0,0 +1,22 @@ X+# Based off of the default elf32 MIPS target. However, we use a seperate X+# script template because the PSP architecture defines sections that normally X+# cannot be overriden here and would normally get absorbed (i.e. X+# .rodata.sceModuleInfo would be absorbed into .rodata). X+ X+EMBEDDED=yes X+. ${srcdir}/emulparams/elf32lmip.sh X+unset NONPAGED_TEXT_START_ADDR X+unset SHLIB_TEXT_START_ADDR X+unset COMMONPAGESIZE X+ X+SCRIPT_NAME=elf_psp X+TEXT_START_ADDR=0x08900000 X+MAXPAGESIZE=256 X+ARCH="mips:allegrex" X+MACHINE= X+TEMPLATE_NAME=elf32 X+GENERATE_SHLIB_SCRIPT=yes X+DYNAMIC_LINK=FALSE X+ X+# Discard the .comment and .pdr sections. X+OTHER_SECTIONS="/DISCARD/ : { *(.comment) *(.pdr) }" END-of-psptoolchain-binutils/files/patch-ld-emulparams-elf_mipsallegrexel_psp.sh echo x - psptoolchain-binutils/files/patch-ld-scripttempl-elf_psp.sc sed 's/^X//' >psptoolchain-binutils/files/patch-ld-scripttempl-elf_psp.sc << 'END-of-psptoolchain-binutils/files/patch-ld-scripttempl-elf_psp.sc' X--- ld/scripttempl/elf_psp.sc.orig 1970-01-01 01:00:00.000000000 +0100 X+++ ld/scripttempl/elf_psp.sc 2006-05-09 02:55:36.000000000 +0100 X@@ -0,0 +1,496 @@ X+# X+# Unusual variables checked by this code: X+# NOP - four byte opcode for no-op (defaults to 0) X+# NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not X+# empty. X+# SMALL_DATA_CTOR - .ctors contains small data. X+# SMALL_DATA_DTOR - .dtors contains small data. X+# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start X+# INITIAL_READONLY_SECTIONS - at start of text segment X+# OTHER_READONLY_SECTIONS - other than .text .init .rodata ... X+# (e.g., .PARISC.milli) X+# OTHER_TEXT_SECTIONS - these get put in .text when relocating X+# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ... X+# (e.g., .PARISC.global) X+# OTHER_RELRO_SECTIONS - other than .data.rel.ro ... X+# (e.g. PPC32 .fixup, .got[12]) X+# OTHER_BSS_SECTIONS - other than .bss .sbss ... X+# OTHER_SECTIONS - at the end X+# EXECUTABLE_SYMBOLS - symbols that must be defined for an X+# executable (e.g., _DYNAMIC_LINK) X+# TEXT_START_ADDR - the first byte of the text segment, after any X+# headers. X+# TEXT_BASE_ADDRESS - the first byte of the text segment. X+# TEXT_START_SYMBOLS - symbols that appear at the start of the X+# .text section. X+# DATA_START_SYMBOLS - symbols that appear at the start of the X+# .data section. X+# OTHER_GOT_SYMBOLS - symbols defined just before .got. X+# OTHER_GOT_SECTIONS - sections just after .got. X+# OTHER_SDATA_SECTIONS - sections just after .sdata. X+# OTHER_BSS_SYMBOLS - symbols that appear at the start of the X+# .bss section besides __bss_start. X+# DATA_PLT - .plt should be in data segment, not text segment. X+# PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement. X+# BSS_PLT - .plt should be in bss segment X+# TEXT_DYNAMIC - .dynamic in text segment, not data segment. X+# EMBEDDED - whether this is for an embedded system. X+# SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set X+# start address of shared library. X+# INPUT_FILES - INPUT command of files to always include X+# WRITABLE_RODATA - if set, the .rodata section should be writable X+# INIT_START, INIT_END - statements just before and just after X+# combination of .init sections. X+# FINI_START, FINI_END - statements just before and just after X+# combination of .fini sections. X+# STACK_ADDR - start of a .stack section. X+# OTHER_END_SYMBOLS - symbols to place right at the end of the script. X+# SEPARATE_GOTPLT - if set, .got.plt should be separate output section, X+# so that .got can be in the RELRO area. It should be set to X+# the number of bytes in the beginning of .got.plt which can be X+# in the RELRO area as well. X+# X+# When adding sections, do note that the names of some sections are used X+# when specifying the start address of the next. X+# X+ X+# Many sections come in three flavours. There is the 'real' section, X+# like ".data". Then there are the per-procedure or per-variable X+# sections, generated by -ffunction-sections and -fdata-sections in GCC, X+# and useful for --gc-sections, which for a variable "foo" might be X+# ".data.foo". Then there are the linkonce sections, for which the linker X+# eliminates duplicates, which are named like ".gnu.linkonce.d.foo". X+# The exact correspondences are: X+# X+# Section Linkonce section X+# .text .gnu.linkonce.t.foo X+# .rodata .gnu.linkonce.r.foo X+# .data .gnu.linkonce.d.foo X+# .bss .gnu.linkonce.b.foo X+# .sdata .gnu.linkonce.s.foo X+# .sbss .gnu.linkonce.sb.foo X+# .sdata2 .gnu.linkonce.s2.foo X+# .sbss2 .gnu.linkonce.sb2.foo X+# .debug_info .gnu.linkonce.wi.foo X+# .tdata .gnu.linkonce.td.foo X+# .tbss .gnu.linkonce.tb.foo X+# X+# Each of these can also have corresponding .rel.* and .rela.* sections. X+ X+test -z "$ENTRY" && ENTRY=_start X+test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT} X+test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT} X+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi X+test -z "${ELFSIZE}" && ELFSIZE=32 X+test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8" X+test "$LD_FLAG" = "N" && DATA_ADDR=. X+test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE="" X+test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE="" X+test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT X+DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))" X+DATA_SEGMENT_RELRO_END="" X+DATA_SEGMENT_RELRO_GOTPLT_END="" X+DATA_SEGMENT_END="" X+if test -n "${COMMONPAGESIZE}"; then X+ DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) & (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})" X+ DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);" X+ if test -n "${SEPARATE_GOTPLT}"; then X+ DATA_SEGMENT_RELRO_GOTPLT_END=". = DATA_SEGMENT_RELRO_END (${SEPARATE_GOTPLT}, .);" X+ else X+ DATA_SEGMENT_RELRO_END=". = DATA_SEGMENT_RELRO_END (0, .);" X+ fi X+fi X+INTERP=".interp ${RELOCATING-0} : { *(.interp) }" X+PLT=".plt ${RELOCATING-0} : { *(.plt) }" X+if test -z "$GOT"; then X+ if test -z "$SEPARATE_GOTPLT"; then X+ GOT=".got ${RELOCATING-0} : { *(.got.plt) *(.got) }" X+ else X+ GOT=".got ${RELOCATING-0} : { *(.got) }" X+ GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}} X+ .got.plt ${RELOCATING-0} : { *(.got.plt) }" X+ fi X+fi X+DYNAMIC=".dynamic ${RELOCATING-0} : { *(.dynamic) }" X+RODATA=".rodata ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }" X+DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }" X+STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }" X+if test -z "${NO_SMALL_DATA}"; then X+ SBSS=".sbss ${RELOCATING-0} : X+ { X+ ${RELOCATING+PROVIDE (__sbss_start = .);} X+ ${RELOCATING+PROVIDE (___sbss_start = .);} X+ ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)} X+ *(.dynsbss) X+ *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*}) X+ *(.scommon) X+ ${RELOCATING+PROVIDE (__sbss_end = .);} X+ ${RELOCATING+PROVIDE (___sbss_end = .);} X+ }" X+ SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }" X+ SDATA="/* We want the small data sections together, so single-instruction offsets X+ can access them all, and initialized data all before uninitialized, so X+ we can shorten the on-disk segment size. */ X+ .sdata ${RELOCATING-0} : X+ { X+ ${RELOCATING+${SDATA_START_SYMBOLS}} X+ ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)} X+ *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*}) X+ }" X+ SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }" X+ REL_SDATA=".rel.sdata ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) } X+ .rela.sdata ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }" X+ REL_SBSS=".rel.sbss ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) } X+ .rela.sbss ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }" X+ REL_SDATA2=".rel.sdata2 ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) } X+ .rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }" X+ REL_SBSS2=".rel.sbss2 ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) } X+ .rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }" X+else X+ NO_SMALL_DATA=" " X+fi X+test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" " X+CTOR=".ctors ${CONSTRUCTING-0} : X+ { X+ ${CONSTRUCTING+${CTOR_START}} X+ /* gcc uses crtbegin.o to find the start of X+ the constructors, so we make sure it is X+ first. Because this is a wildcard, it X+ doesn't matter if the user does not X+ actually link against crtbegin.o; the X+ linker won't look for a file to match a X+ wildcard. The wildcard also means that it X+ doesn't matter which directory crtbegin.o X+ is in. */ X+ X+ KEEP (*crtbegin*.o(.ctors)) X+ X+ /* We don't want to include the .ctor section from X+ from the crtend.o file until after the sorted ctors. X+ The .ctor section from the crtend file contains the X+ end of ctors marker and it must be last */ X+ X+ KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors)) X+ KEEP (*(SORT(.ctors.*))) X+ KEEP (*(.ctors)) X+ ${CONSTRUCTING+${CTOR_END}} X+ }" X+DTOR=".dtors ${CONSTRUCTING-0} : X+ { X+ ${CONSTRUCTING+${DTOR_START}} X+ KEEP (*crtbegin*.o(.dtors)) X+ KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors)) X+ KEEP (*(SORT(.dtors.*))) X+ KEEP (*(.dtors)) X+ ${CONSTRUCTING+${DTOR_END}} X+ }" X+STACK=" .stack ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} : X+ { X+ ${RELOCATING+_stack = .;} X+ *(.stack) X+ }" X+ X+# if this is for an embedded system, don't add SIZEOF_HEADERS. X+if [ -z "$EMBEDDED" ]; then X+ test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS" X+else X+ test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}" X+fi X+ X+cat <<EOF X+OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}", X+ "${LITTLE_OUTPUT_FORMAT}") X+OUTPUT_ARCH(${OUTPUT_ARCH}) X+ENTRY(${ENTRY}) X+ X+${RELOCATING+${LIB_SEARCH_DIRS}} X+${RELOCATING+/* Do we need any of these for elf? X+ __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}} */} X+${RELOCATING+${EXECUTABLE_SYMBOLS}} X+${RELOCATING+${INPUT_FILES}} X+${RELOCATING- /* For some reason, the Solaris linker makes bad executables X+ if gld -r is used and the intermediate file has sections starting X+ at non-zero addresses. Could be a Solaris ld bug, could be a GNU ld X+ bug. But for now assigning the zero vmas works. */} X+ X+SECTIONS X+{ X+ /* Read-only sections, merged into text segment: */ X+ ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}} X+ ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}} X+ ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}} X+ ${CREATE_SHLIB-${INTERP}} X+ ${INITIAL_READONLY_SECTIONS} X+ ${TEXT_DYNAMIC+${DYNAMIC}} X+ .hash ${RELOCATING-0} : { *(.hash) } X+ .dynsym ${RELOCATING-0} : { *(.dynsym) } X+ .dynstr ${RELOCATING-0} : { *(.dynstr) } X+ .gnu.version ${RELOCATING-0} : { *(.gnu.version) } X+ .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) } X+ .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) } X+ X+EOF X+if [ "x$COMBRELOC" = x ]; then X+ COMBRELOCCAT=cat X+else X+ COMBRELOCCAT="cat > $COMBRELOC" X+fi X+eval $COMBRELOCCAT <<EOF X+ .rel.init ${RELOCATING-0} : { *(.rel.init) } X+ .rela.init ${RELOCATING-0} : { *(.rela.init) } X+ .rel.text ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) } X+ .rela.text ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) } X+ .rel.fini ${RELOCATING-0} : { *(.rel.fini) } X+ .rela.fini ${RELOCATING-0} : { *(.rela.fini) } X+ X+ /* PSP-specific relocations. */ X+ .rel.sceStub.text ${RELOCATING-0} : { *(.rel.sceStub.text) *(SORT(.rel.sceStub.text.*)) } X+ .rel.lib.ent.top ${RELOCATING-0} : { *(.rel.lib.ent.top) } X+ .rel.lib.ent ${RELOCATING-0} : { *(.rel.lib.ent) } X+ .rel.lib.ent.btm ${RELOCATING-0} : { *(.rel.lib.ent.btm) } X+ .rel.lib.stub.top ${RELOCATING-0} : { *(.rel.lib.stub.top) } X+ .rel.lib.stub ${RELOCATING-0} : { *(.rel.lib.stub) } X+ .rel.lib.stub.btm ${RELOCATING-0} : { *(.rel.lib.stub.btm) } X+ .rel.rodata.sceModuleInfo ${RELOCATING-0} : { *(.rel.rodata.sceModuleInfo) } X+ .rel.rodata.sceResident ${RELOCATING-0} : { *(.rel.rodata.sceResident) } X+ .rel.rodata.sceNid ${RELOCATING-0} : { *(.rel.rodata.sceNid) } X+ .rel.rodata.sceVstub ${RELOCATING-0} : { *(.rel.rodata.sceVstub) *(SORT(.rel.rodata.sceVstub.*)) } X+ X+ .rel.rodata ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) } X+ .rela.rodata ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) } X+ ${OTHER_READONLY_RELOC_SECTIONS} X+ .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) } X+ .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) } X+ .rel.data ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) } X+ .rela.data ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) } X+ .rel.tdata ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) } X+ .rela.tdata ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) } X+ .rel.tbss ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) } X+ .rela.tbss ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) } X+ .rel.ctors ${RELOCATING-0} : { *(.rel.ctors) } X+ .rela.ctors ${RELOCATING-0} : { *(.rela.ctors) } X+ .rel.dtors ${RELOCATING-0} : { *(.rel.dtors) } X+ .rela.dtors ${RELOCATING-0} : { *(.rela.dtors) } X+ .rel.got ${RELOCATING-0} : { *(.rel.got) } X+ .rela.got ${RELOCATING-0} : { *(.rela.got) } X+ ${OTHER_GOT_RELOC_SECTIONS} X+ ${REL_SDATA} X+ ${REL_SBSS} X+ ${REL_SDATA2} X+ ${REL_SBSS2} X+ .rel.bss ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) } X+ .rela.bss ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) } X+EOF X+if [ -n "$COMBRELOC" ]; then X+cat <<EOF X+ .rel.dyn ${RELOCATING-0} : X+ { X+EOF X+sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/ \1/' $COMBRELOC X+cat <<EOF X+ } X+ .rela.dyn ${RELOCATING-0} : X+ { X+EOF X+sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/ \1/' $COMBRELOC X+cat <<EOF X+ } X+EOF X+fi X+cat <<EOF X+ .rel.plt ${RELOCATING-0} : { *(.rel.plt) } X+ .rela.plt ${RELOCATING-0} : { *(.rela.plt) } X+ ${OTHER_PLT_RELOC_SECTIONS} X+ X+ .init ${RELOCATING-0} : X+ { X+ ${RELOCATING+${INIT_START}} X+ KEEP (*(.init)) X+ ${RELOCATING+${INIT_END}} X+ } =${NOP-0} X+ X+ ${DATA_PLT-${BSS_PLT-${PLT}}} X+ .text ${RELOCATING-0} : X+ { X+ ${RELOCATING+${TEXT_START_SYMBOLS}} X+ *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*}) X+ KEEP (*(.text.*personality*)) X+ /* .gnu.warning sections are handled specially by elf32.em. */ X+ *(.gnu.warning) X+ ${RELOCATING+${OTHER_TEXT_SECTIONS}} X+ } =${NOP-0} X+ .fini ${RELOCATING-0} : X+ { X+ ${RELOCATING+${FINI_START}} X+ KEEP (*(.fini)) X+ ${RELOCATING+${FINI_END}} X+ } =${NOP-0} X+ X+ /* PSP library stub functions. */ X+ .sceStub.text ${RELOCATING-0} : { *(.sceStub.text) *(SORT(.sceStub.text.*)) } X+ X+ ${RELOCATING+PROVIDE (__etext = .);} X+ ${RELOCATING+PROVIDE (_etext = .);} X+ ${RELOCATING+PROVIDE (etext = .);} X+ X+ /* PSP library entry table and library stub table. */ X+ .lib.ent.top ${RELOCATING-0} : { *(.lib.ent.top) } X+ .lib.ent ${RELOCATING-0} : { *(.lib.ent) } X+ .lib.ent.btm ${RELOCATING-0} : { *(.lib.ent.btm) } X+ X+ .lib.stub.top ${RELOCATING-0} : { *(.lib.stub.top) } X+ .lib.stub ${RELOCATING-0} : { *(.lib.stub) } X+ .lib.stub.btm ${RELOCATING-0} : { *(.lib.stub.btm) } X+ X+ /* PSP read-only data for module info, NIDs, and Vstubs. The X+ .rodata.sceModuleInfo section must appear before the .rodata section X+ otherwise it would get absorbed into .rodata and the PSP bootloader X+ would be unable to locate the module info structure. */ X+ .rodata.sceModuleInfo ${RELOCATING-0} : { *(.rodata.sceModuleInfo) } X+ .rodata.sceResident ${RELOCATING-0} : { *(.rodata.sceResident) } X+ .rodata.sceNid ${RELOCATING-0} : { *(.rodata.sceNid) } X+ .rodata.sceVstub ${RELOCATING-0} : { *(.rodata.sceVstub) *(SORT(.rodata.sceVstub.*)) } X+ X+ ${WRITABLE_RODATA-${RODATA}} X+ .rodata1 ${RELOCATING-0} : { *(.rodata1) } X+ ${CREATE_SHLIB-${SDATA2}} X+ ${CREATE_SHLIB-${SBSS2}} X+ ${OTHER_READONLY_SECTIONS} X+ .eh_frame_hdr : { *(.eh_frame_hdr) } X+ .eh_frame ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) } X+ .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } X+ X+ /* Adjust the address for the data segment. We want to adjust up to X+ the same address within the page on the next page up. */ X+ ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}} X+ ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}} X+ ${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}} X+ X+ /* Exception handling */ X+ .eh_frame ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) } X+ .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } X+ X+ /* Thread Local Storage sections */ X+ .tdata ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) } X+ .tbss ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} } X+ X+ /* Ensure the __preinit_array_start label is properly aligned. We X+ could instead move the label definition inside the section, but X+ the linker would then create the section even if it turns out to X+ be empty, which isn't pretty. */ X+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} X+ ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = .);}} X+ .preinit_array ${RELOCATING-0} : { KEEP (*(.preinit_array)) } X+ ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}} X+ X+ ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}} X+ .init_array ${RELOCATING-0} : { KEEP (*(.init_array)) } X+ ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}} X+ X+ ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}} X+ .fini_array ${RELOCATING-0} : { KEEP (*(.fini_array)) } X+ ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}} X+ X+ ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}}} X+ ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}}} X+ .jcr ${RELOCATING-0} : { KEEP (*(.jcr)) } X+ X+ ${RELOCATING+${DATARELRO}} X+ ${OTHER_RELRO_SECTIONS} X+ ${TEXT_DYNAMIC-${DYNAMIC}} X+ ${NO_SMALL_DATA+${RELRO_NOW+${GOT}}} X+ ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}}}} X+ ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}}}} X+ ${RELOCATING+${DATA_SEGMENT_RELRO_END}} X+ ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}}}} X+ X+ ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}}} X+ X+ .data ${RELOCATING-0} : X+ { X+ ${RELOCATING+${DATA_START_SYMBOLS}} X+ *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*}) X+ KEEP (*(.gnu.linkonce.d.*personality*)) X+ ${CONSTRUCTING+SORT(CONSTRUCTORS)} X+ } X+ .data1 ${RELOCATING-0} : { *(.data1) } X+ ${WRITABLE_RODATA+${RODATA}} X+ ${OTHER_READWRITE_SECTIONS} X+ ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}}} X+ ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}}} X+ ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}}} X+ ${RELOCATING+${OTHER_GOT_SYMBOLS}} X+ ${NO_SMALL_DATA-${GOT}} X+ ${OTHER_GOT_SECTIONS} X+ ${SDATA} X+ ${OTHER_SDATA_SECTIONS} X+ ${RELOCATING+_edata = .;} X+ ${RELOCATING+PROVIDE (edata = .);} X+ ${RELOCATING+__bss_start = .;} X+ ${RELOCATING+${OTHER_BSS_SYMBOLS}} X+ ${SBSS} X+ ${BSS_PLT+${PLT}} X+ .bss ${RELOCATING-0} : X+ { X+ *(.dynbss) X+ *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*}) X+ *(COMMON) X+ /* Align here to ensure that the .bss section occupies space up to X+ _end. Align after .bss to ensure correct alignment even if the X+ .bss section disappears because there are no input sections. */ X+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} X+ } X+ ${OTHER_BSS_SECTIONS} X+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} X+ ${RELOCATING+_end = .;} X+ ${RELOCATING+${OTHER_BSS_END_SYMBOLS}} X+ ${RELOCATING+PROVIDE (end = .);} X+ ${RELOCATING+${DATA_SEGMENT_END}} X+ X+ /* Stabs debugging sections. */ X+ .stab 0 : { *(.stab) } X+ .stabstr 0 : { *(.stabstr) } X+ .stab.excl 0 : { *(.stab.excl) } X+ .stab.exclstr 0 : { *(.stab.exclstr) } X+ .stab.index 0 : { *(.stab.index) } X+ .stab.indexstr 0 : { *(.stab.indexstr) } X+ X+ .comment 0 : { *(.comment) } X+ X+ /* DWARF debug sections. X+ Symbols in the DWARF debugging sections are relative to the beginning X+ of the section so we begin them at 0. */ X+ X+ /* DWARF 1 */ X+ .debug 0 : { *(.debug) } X+ .line 0 : { *(.line) } X+ X+ /* GNU DWARF 1 extensions */ X+ .debug_srcinfo 0 : { *(.debug_srcinfo) } X+ .debug_sfnames 0 : { *(.debug_sfnames) } X+ X+ /* DWARF 1.1 and DWARF 2 */ X+ .debug_aranges 0 : { *(.debug_aranges) } X+ .debug_pubnames 0 : { *(.debug_pubnames) } X+ X+ /* DWARF 2 */ X+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } X+ .debug_abbrev 0 : { *(.debug_abbrev) } X+ .debug_line 0 : { *(.debug_line) } X+ .debug_frame 0 : { *(.debug_frame) } X+ .debug_str 0 : { *(.debug_str) } X+ .debug_loc 0 : { *(.debug_loc) } X+ .debug_macinfo 0 : { *(.debug_macinfo) } X+ X+ /* SGI/MIPS DWARF 2 extensions */ X+ .debug_weaknames 0 : { *(.debug_weaknames) } X+ .debug_funcnames 0 : { *(.debug_funcnames) } X+ .debug_typenames 0 : { *(.debug_typenames) } X+ .debug_varnames 0 : { *(.debug_varnames) } X+ X+ ${STACK_ADDR+${STACK}} X+ ${OTHER_SECTIONS} X+ ${RELOCATING+${OTHER_END_SYMBOLS}} X+ ${RELOCATING+${STACKNOTE}} X+} X+EOF END-of-psptoolchain-binutils/files/patch-ld-scripttempl-elf_psp.sc echo x - psptoolchain-binutils/files/patch-opcodes-mips-opc.c sed 's/^X//' >psptoolchain-binutils/files/patch-opcodes-mips-opc.c << 'END-of-psptoolchain-binutils/files/patch-opcodes-mips-opc.c' X--- opcodes/mips-opc.c.orig 2005-03-03 11:49:50.000000000 +0000 X+++ opcodes/mips-opc.c 2006-05-09 02:55:36.000000000 +0100 X@@ -109,6 +109,7 @@ X #define N5 (INSN_5400 | INSN_5500) X #define N54 INSN_5400 X #define N55 INSN_5500 X+#define AL INSN_ALLEGREX X X #define G1 (T3 \ X ) X@@ -271,6 +272,7 @@ X {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, X {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, X {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, X+{"break", "B", 0x0000000d, 0xfc00003f, TRAP, 0, AL }, X {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, X {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, X {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, X@@ -432,7 +434,7 @@ X {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, X {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, X {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, X-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, X+{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3|AL}, X {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 }, X {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 }, X {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, X@@ -443,7 +445,9 @@ X /* cfc2 is at the bottom of the table. */ X {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, X {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, X+{"clo", "d,s", 0x00000017, 0xfc1f07ff, WR_d|RD_s, 0, AL }, X {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, X+{"clz", "d,s", 0x00000016, 0xfc1f07ff, WR_d|RD_s, 0, AL }, X {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, X {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, X {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, X@@ -465,13 +469,15 @@ X {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, X {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, X {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, X+{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL }, X {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, X {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, X {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, X {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, X+{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL }, X {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, X {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, X-{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, X+{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL }, X {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, X {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, X /* dctr and dctw are used on the r5000. */ X@@ -558,7 +564,7 @@ X {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, X {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, X {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, X-{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, X+{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5|AL }, X {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, X {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, X {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, X@@ -595,8 +601,8 @@ X {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, X {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, X {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, X-{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, X-{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, X+{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32|AL }, X+{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33|AL }, X {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 }, X {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 }, X {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, X@@ -605,7 +611,7 @@ X {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, X {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, X {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, X-{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, X+{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33|AL }, X {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, X {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I33 }, X {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ X@@ -639,18 +645,10 @@ X {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, X {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, X {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, X-{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, X-{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, X-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, X-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, X-{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ X-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, X-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, X-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, X-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, X-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, X-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, X-{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, X+/* ldc1 is at the bottom of the table. */ X+/* ldc2 is at the bottom of the table. */ X+/* ldc3 is at the bottom of the table. */ X+{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL }, X {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, X {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, X {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, X@@ -680,8 +678,7 @@ X {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, X {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ X {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, X-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, X-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, X+/* lwc2 is at the bottom of the table. */ X {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, X {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, X {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, X@@ -713,10 +710,12 @@ X {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 }, X {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, X {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, X+{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, X {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55}, X {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, X {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, X {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, X+{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, X {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55}, X {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, X {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, X@@ -739,7 +738,7 @@ X /* mfhc2 is at the bottom of the table. */ X {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, X {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, X-{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, X+{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5|AL }, X {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, X {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, X {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, X@@ -756,7 +755,7 @@ X {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, X {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, X {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, X-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, X+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL }, X {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, X {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, X {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, X@@ -769,7 +768,7 @@ X {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, X {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, X {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, X-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, X+{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL }, X {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, X {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, X {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, X@@ -786,8 +785,10 @@ X {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 }, X {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, X {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, X+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, X {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, X {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, X+{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL }, X {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, X {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, X {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, X@@ -802,7 +803,7 @@ X /* mthc2 is at the bottom of the table. */ X {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, X {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, X-{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, X+{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5|AL }, X {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, X {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, X {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, X@@ -936,13 +937,13 @@ X {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, X {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, X {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, X-{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33 }, X-{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33 }, X-{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33 }, X-{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33 }, X-{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33 }, X-{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33 }, X-{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 }, X+{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|AL }, X+{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|AL }, X+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL }, X+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL }, X+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL }, X+{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL }, X+{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|AL }, X {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 }, X {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 }, X {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, X@@ -974,24 +975,17 @@ X {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, X {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, X {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, X-{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, X-{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, X-{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, X-{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, X-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, X-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, X-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, X-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, X-{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, X-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, X-{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, X-{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, X+/* sdc1 is at the bottom of the table. */ X+/* sdc2 is at the bottom of the table. */ X+/* sdc3 is at the bottom of the table. */ X+/* s.d (sdc1 is at the bottom of the table. */ X+{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3|AL }, X {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, X {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, X {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, X {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4 }, X-{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, X-{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, X+{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33|AL }, X+{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33|AL }, X {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, X {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, X {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, X@@ -1083,8 +1077,7 @@ X {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, X {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ X {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, X-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, X-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, X+/* swc2 is at the bottom of the table. */ X {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, X {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, X {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, X@@ -1169,7 +1162,8 @@ X {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, X {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, X {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, X-{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, X+{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33|AL }, X+{"wsbw", "d,t", 0x7c0000e0, 0xffe007ff, WR_d|RD_t, 0, AL }, X {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, X {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, X {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, X@@ -1179,6 +1173,319 @@ X {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, X {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, X X+/* Sony Allegrex CPU core. */ X+{"bitrev", "d,t", 0x7c000520, 0xffe007ff, WR_d|RD_t, 0, AL }, X+{"mfic", "t,G", 0x70000024, 0xffe007ff, LCD|WR_t|RD_C0, 0, AL }, X+{"mtic", "t,G", 0x70000026, 0xffe007ff, COD|RD_t|WR_C0, 0, AL }, X+ X+/* Sony Allegrex VFPU instructions. */ X+{"bvf", "?c,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL }, X+{"bvfl", "?c,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL }, X+{"bvt", "?c,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, AL }, X+{"bvtl", "?c,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, AL }, X+{"lv.s", "?m0x,?o(b)", 0xc8000000, 0xfc000000, CLD|RD_s|WR_CC, 0, AL }, X+{"lv.s", "?m0x,A(b)", 0, (int) M_LV_Q_AB, INSN_MACRO, 0, AL }, X+{"ulv.s", "?m0x,o(b)", 0, (int) M_ULV_S, INSN_MACRO, 0, AL }, X+{"lv.q", "?n3x,?o(b)", 0xd8000000, 0xfc000002, CLD|RD_s|WR_CC, 0, AL }, X+{"lv.q", "?n3x,A(b)", 0, (int) M_LV_Q_AB_2, INSN_MACRO, 0, AL }, X+{"ulv.q", "?n3x,?o(b)", 0, (int) M_ULV_Q, INSN_MACRO, 0, AL }, X+{"ulv.q", "?n3x,A(b)", 0, (int) M_ULV_Q_AB, INSN_MACRO, 0, AL }, X+{"lvi.s", "?t0x,l?y0", 0, (int) M_LVI_S, INSN_MACRO, 0, AL }, X+{"lvi.p", "?t1x,?[l?y0,l?y1?]", 0, (int) M_LVI_P, INSN_MACRO, 0, AL }, X+{"lvi.t", "?t2x,?[l?y0,l?y1,l?y2?]", 0, (int) M_LVI_T, INSN_MACRO, 0, AL }, X+{"lvi.q", "?t3x,?[l?y0,l?y1,l?y2,l?y3?]", 0, (int) M_LVI_Q, INSN_MACRO, 0, AL }, X+{"lvhi.s", "?t0x,?[?u?y0,?u?y1?]", 0, (int) M_LVHI_S, INSN_MACRO, 0, AL }, X+{"lvhi.p", "?t1x,?[?u?y0,?u?y1,?u?y2,?u?y3?]", 0, (int) M_LVHI_P, INSN_MACRO, 0, AL }, X+{"sv.s", "?m0x,?o(b)", 0xe8000000, 0xfc000000, SM|RD_s|RD_C2, 0, AL }, X+{"sv.s", "?m0x,A(b)", 0, (int) M_SV_S_AB, INSN_MACRO, 0, AL }, X+{"usv.s", "?m0x,o(b)", 0, (int) M_USV_S, INSN_MACRO, 0, AL }, X+{"sv.q", "?n3x,?o(b)", 0xf8000000, 0xfc000002, SM|RD_s|RD_C2, 0, AL }, X+{"sv.q", "?n3x,?o(b),?z", 0xf8000000, 0xfc000000, SM|RD_s|RD_C2, 0, AL }, X+{"sv.q", "?n3x,A(b)", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL }, X+{"sv.q", "?n3x,A(b),?z", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL }, X+{"sv.q", "?n3x,A,?z", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL }, X+{"usv.q", "?n3x,?o(b)", 0, (int) M_USV_Q, INSN_MACRO, 0, AL }, X+{"usv.q", "?n3x,A(b)", 0, (int) M_USV_Q_AB, INSN_MACRO, 0, AL }, X+{"vwb.q", "?n3x,?o(b)", 0xf8000002, 0xfc000002, SM|RD_s|RD_C2, 0, AL }, X+{"lvl.q", "?n3x,?o(b)", 0xd4000000, 0xfc000002, CLD|RD_s|WR_CC, 0, AL }, X+{"lvl.q", "?n3x,A(b)", 0, (int) M_LVL_Q_AB, INSN_MACRO, 0, AL }, X+{"lvr.q", "?n3x,?o(b)", 0xd4000002, 0xfc000002, CLD|RD_s|WR_CC, 0, AL }, X+{"lvr.q", "?n3x,A(b)", 0, (int) M_LVR_Q_AB, INSN_MACRO, 0, AL }, X+{"svl.q", "?n3x,?o(b)", 0xf4000000, 0xfc000002, SM|RD_s|RD_C2, 0, AL }, X+{"svl.q", "?n3x,A(b)", 0, (int) M_SVL_Q_AB, INSN_MACRO, 0, AL }, X+{"svr.q", "?n3x,?o(b)", 0xf4000002, 0xfc000002, SM|RD_s|RD_C2, 0, AL }, X+{"svr.q", "?n3x,A(b)", 0, (int) M_SVR_Q_AB, INSN_MACRO, 0, AL }, X+{"mtv", "t,?d0z", 0x48e00000, 0xffe0ff80, LCD|WR_t|WR_C2, 0, AL }, X+{"mfv", "t,?d0z", 0x48600000, 0xffe0ff80, COD|RD_t|WR_CC|RD_C2, 0, AL }, X+{"mtvc", "t,?q", 0x48e00000, 0xffe0ff00, LCD|WR_t|WR_C2, 0, AL }, X+{"mfvc", "t,?q", 0x48600000, 0xffe0ff00, COD|RD_t|WR_CC|RD_C2, 0, AL }, X+{"vmtvc", "?q,?s0y", 0xd0510000, 0xffff8000, WR_C2, 0, AL }, X+{"vmfvc", "?d0z,?r", 0xd0500000, 0xffff0080, RD_C2, 0, AL }, X+{"vadd.q", "?d3d,?s3s,?t3t", 0x60008080, 0xff808080, RD_C2, 0, AL }, X+{"vsub.q", "?d3d,?s3s,?t3t", 0x60808080, 0xff808080, RD_C2, 0, AL }, X+{"vdiv.q", "?x3z,?s3y,?t3x", 0x63808080, 0xff808080, RD_C2, 0, AL }, X+{"vmul.q", "?d3d,?s3s,?t3t", 0x64008080, 0xff808080, RD_C2, 0, AL }, X+{"vdot.q", "?d0d,?s3s,?t3t", 0x64808080, 0xff808080, RD_C2, 0, AL }, X+{"vscl.q", "?d3d,?s3s,?t0x", 0x65008080, 0xff808080, RD_C2, 0, AL }, X+{"vhdp.q", "?d0d,?s3y,?t3t", 0x66008080, 0xff808080, RD_C2, 0, AL }, X+{"vcmp.q", "?f2,?s3s,?t3t", 0x6c008080, 0xff8080f0, RD_C2, 0, AL }, X+{"vcmp.q", "?f1,?s3s", 0x6c008080, 0xffff80f0, RD_C2, 0, AL }, X+{"vcmp.q", "?f0", 0x6c008080, 0xfffffff0, RD_C2, 0, AL }, X+{"vmin.q", "?d3d,?s3s,?t3t", 0x6d008080, 0xff808080, RD_C2, 0, AL }, X+{"vmax.q", "?d3d,?s3s,?t3t", 0x6d808080, 0xff808080, RD_C2, 0, AL }, X+{"vsgn.q", "?d3d,?s3s", 0xd04a8080, 0xffff8080, RD_C2, 0, AL }, X+{"vcst.q", "?d3d,?a", 0xd0608080, 0xffe0ff80, RD_C2, 0, AL }, X+{"vscmp.q", "?d3d,?s3s,?t3t", 0x6e808080, 0xff808080, RD_C2, 0, AL }, X+{"vsge.q", "?d3d,?s3s,?t3t", 0x6f008080, 0xff808080, RD_C2, 0, AL }, X+{"vslt.q", "?d3d,?s3s,?t3t", 0x6f808080, 0xff808080, RD_C2, 0, AL }, X+{"vi2uc.q", "?d0m,?s3w", 0xd03c8080, 0xffff8080, RD_C2, 0, AL }, X+{"vi2c.q", "?d0m,?s3w", 0xd03d8080, 0xffff8080, RD_C2, 0, AL }, X+{"vi2us.q", "?d1m,?s3w", 0xd03e8080, 0xffff8080, RD_C2, 0, AL }, X+{"vi2s.q", "?d1m,?s3w", 0xd03f8080, 0xffff8080, RD_C2, 0, AL }, X+{"vmov.q", "?d3d,?s3s", 0xd0008080, 0xffff8080, RD_C2, 0, AL }, X+{"vabs.q", "?d3d,?s3w", 0xd0018080, 0xffff8080, RD_C2, 0, AL }, X+{"vneg.q", "?d3d,?s3w", 0xd0028080, 0xffff8080, RD_C2, 0, AL }, X+{"vidt.q", "?d3d", 0xd0038080, 0xffffff80, RD_C2, 0, AL }, X+{"vsat0.q", "?d3z,?s3s", 0xd0048080, 0xffff8080, RD_C2, 0, AL }, X+{"vsat1.q", "?d3z,?s3s", 0xd0058080, 0xffff8080, RD_C2, 0, AL }, X+{"vzero.q", "?d3d", 0xd0068080, 0xffffff80, RD_C2, 0, AL }, X+{"vone.q", "?d3d", 0xd0078080, 0xffffff80, RD_C2, 0, AL }, X+{"vrcp.q", "?x3z,?s3y", 0xd0108080, 0xffff8080, RD_C2, 0, AL }, X+{"vrsq.q", "?x3z,?s3y", 0xd0118080, 0xffff8080, RD_C2, 0, AL }, X+{"vsin.q", "?x3z,?s3y", 0xd0128080, 0xffff8080, RD_C2, 0, AL }, X+{"vcos.q", "?x3z,?s3y", 0xd0138080, 0xffff8080, RD_C2, 0, AL }, X+{"vexp2.q", "?x3z,?s3y", 0xd0148080, 0xffff8080, RD_C2, 0, AL }, X+{"vlog2.q", "?x3z,?s3y", 0xd0158080, 0xffff8080, RD_C2, 0, AL }, X+{"vsqrt.q", "?x3z,?s3y", 0xd0168080, 0xffff8080, RD_C2, 0, AL }, X+{"vasin.q", "?x3z,?s3y", 0xd0178080, 0xffff8080, RD_C2, 0, AL }, X+{"vnrcp.q", "?x3z,?s3y", 0xd0188080, 0xffff8080, RD_C2, 0, AL }, X+{"vnsin.q", "?x3z,?s3y", 0xd01a8080, 0xffff8080, RD_C2, 0, AL }, X+{"vrexp2.q", "?x3z,?s3y", 0xd01c8080, 0xffff8080, RD_C2, 0, AL }, X+{"vrndi.q", "?d3z", 0xd0218080, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf1.q", "?d3z", 0xd0228080, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf2.q", "?d3z", 0xd0238080, 0xffffff80, RD_C2, 0, AL }, X+{"vf2h.q", "?d1m,?s3s", 0xd0328080, 0xffff8080, RD_C2, 0, AL }, X+{"vsrt1.q", "?d3d,?s3s", 0xd0408080, 0xffff8080, RD_C2, 0, AL }, X+{"vsrt2.q", "?d3d,?s3s", 0xd0418080, 0xffff8080, RD_C2, 0, AL }, X+{"vsrt3.q", "?d3d,?s3s", 0xd0488080, 0xffff8080, RD_C2, 0, AL }, X+{"vsrt4.q", "?d3d,?s3s", 0xd0498080, 0xffff8080, RD_C2, 0, AL }, X+{"vbfy1.q", "?d3d,?s3s", 0xd0428080, 0xffff8080, RD_C2, 0, AL }, X+{"vbfy2.q", "?d3d,?s3s", 0xd0438080, 0xffff8080, RD_C2, 0, AL }, X+{"vocp.q", "?d3d,?s3y", 0xd0448080, 0xffff8080, RD_C2, 0, AL }, X+{"vfad.q", "?d0d,?s3s", 0xd0468080, 0xffff8080, RD_C2, 0, AL }, X+{"vavg.q", "?d0d,?s3s", 0xd0478080, 0xffff8080, RD_C2, 0, AL }, X+{"vf2in.q", "?d3m,?s3s,?b", 0xd2008080, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iz.q", "?d3m,?s3s,?b", 0xd2208080, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iu.q", "?d3m,?s3s,?b", 0xd2408080, 0xffe08080, RD_C2, 0, AL }, X+{"vf2id.q", "?d3m,?s3s,?b", 0xd2608080, 0xffe08080, RD_C2, 0, AL }, X+{"vi2f.q", "?d3d,?s3w,?b", 0xd2808080, 0xffe08080, RD_C2, 0, AL }, X+{"vcmov.q", "?d3d,?s3s,?e", 0, (int) M_VCMOV_Q, INSN_MACRO, 0, AL }, X+{"vcmovt.q", "?d3d,?s3s,?e", 0xd2a08080, 0xfff88080, RD_C2, 0, AL }, X+{"vcmovf.q", "?d3d,?s3s,?e", 0xd2a88080, 0xfff88080, RD_C2, 0, AL }, X+{"vmmul.q", "?v7z,?s7y,?t7x", 0xf0008080, 0xff808080, RD_C2, 0, AL }, X+{"vtfm4.q", "?v3z,?s7y,?t3x", 0xf1808080, 0xff808080, RD_C2, 0, AL }, X+{"vhtfm4.q", "?v3z,?s7y,?t3x", 0xf1808000, 0xff808080, RD_C2, 0, AL }, X+{"vmscl.q", "?x7z,?s7y,?t0x", 0xf2008080, 0xff808080, RD_C2, 0, AL }, X+{"vqmul.q", "?v3z,?s3y,?t3x", 0xf2808080, 0xff808080, RD_C2, 0, AL }, X+{"vmmov.q", "?x7z,?s7y", 0xf3808080, 0xffff8080, RD_C2, 0, AL }, X+{"vmidt.q", "?d7z", 0xf3838080, 0xffffff80, RD_C2, 0, AL }, X+{"vmzero.q", "?d7z", 0xf3868080, 0xffffff80, RD_C2, 0, AL }, X+{"vmone.q", "?d7z", 0xf3878080, 0xffffff80, RD_C2, 0, AL }, X+{"vrot.q", "?x3z,?s0y,?w", 0xf3a08080, 0xffe08080, RD_C2, 0, AL }, X+{"vt4444.q", "?d1z,?s3w", 0xd0598080, 0xffff8080, RD_C2, 0, AL }, X+{"vt5551.q", "?d1z,?s3w", 0xd05a8080, 0xffff8080, RD_C2, 0, AL }, X+{"vt5650.q", "?d1z,?s3w", 0xd05b8080, 0xffff8080, RD_C2, 0, AL }, X+{"vadd.t", "?d2d,?s2s,?t2t", 0x60008000, 0xff808080, RD_C2, 0, AL }, X+{"vsub.t", "?d2d,?s2s,?t2t", 0x60808000, 0xff808080, RD_C2, 0, AL }, X+{"vdiv.t", "?x2z,?s2y,?t2x", 0x63808000, 0xff808080, RD_C2, 0, AL }, X+{"vmul.t", "?d2d,?s2s,?t2t", 0x64008000, 0xff808080, RD_C2, 0, AL }, X+{"vdot.t", "?d0d,?s2s,?t2t", 0x64808000, 0xff808080, RD_C2, 0, AL }, X+{"vscl.t", "?d2d,?s2s,?t0x", 0x65008000, 0xff808080, RD_C2, 0, AL }, X+{"vhdp.t", "?d0d,?s2y,?t2t", 0x66008000, 0xff808080, RD_C2, 0, AL }, X+{"vcrs.t", "?d2d,?s2y,?t2x", 0x66808000, 0xff808080, RD_C2, 0, AL }, X+{"vcmp.t", "?f2,?s2s,?t2t", 0x6c008000, 0xff8080f0, RD_C2, 0, AL }, X+{"vcmp.t", "?f1,?s2s", 0x6c008000, 0xffff80f0, RD_C2, 0, AL }, X+{"vcmp.t", "?f0", 0x6c008000, 0xfffffff0, RD_C2, 0, AL }, X+{"vmin.t", "?d2d,?s2s,?t2t", 0x6d008000, 0xff808080, RD_C2, 0, AL }, X+{"vmax.t", "?d2d,?s2s,?t2t", 0x6d808000, 0xff808080, RD_C2, 0, AL }, X+{"vsgn.t", "?d2d,?s2s", 0xd04a8000, 0xffff8080, RD_C2, 0, AL }, X+{"vcst.t", "?d2d,?a", 0xd0608000, 0xffe0ff80, RD_C2, 0, AL }, X+{"vscmp.t", "?d2d,?s2s,?t2t", 0x6e808000, 0xff808080, RD_C2, 0, AL }, X+{"vsge.t", "?d2d,?s2s,?t2t", 0x6f008000, 0xff808080, RD_C2, 0, AL }, X+{"vslt.t", "?d2d,?s2s,?t2t", 0x6f808000, 0xff808080, RD_C2, 0, AL }, X+{"vmov.t", "?d2d,?s2s", 0xd0008000, 0xffff8080, RD_C2, 0, AL }, X+{"vabs.t", "?d2d,?s2w", 0xd0018000, 0xffff8080, RD_C2, 0, AL }, X+{"vneg.t", "?d2d,?s2w", 0xd0028000, 0xffff8080, RD_C2, 0, AL }, X+{"vsat0.t", "?d2z,?s2s", 0xd0048000, 0xffff8080, RD_C2, 0, AL }, X+{"vsat1.t", "?d2z,?s2s", 0xd0058000, 0xffff8080, RD_C2, 0, AL }, X+{"vzero.t", "?d2d", 0xd0068000, 0xffffff80, RD_C2, 0, AL }, X+{"vone.t", "?d2d", 0xd0078000, 0xffffff80, RD_C2, 0, AL }, X+{"vrcp.t", "?x2z,?s2y", 0xd0108000, 0xffff8080, RD_C2, 0, AL }, X+{"vrsq.t", "?x2z,?s2y", 0xd0118000, 0xffff8080, RD_C2, 0, AL }, X+{"vsin.t", "?x2z,?s2y", 0xd0128000, 0xffff8080, RD_C2, 0, AL }, X+{"vcos.t", "?x2z,?s2y", 0xd0138000, 0xffff8080, RD_C2, 0, AL }, X+{"vexp2.t", "?x2z,?s2y", 0xd0148000, 0xffff8080, RD_C2, 0, AL }, X+{"vlog2.t", "?x2z,?s2y", 0xd0158000, 0xffff8080, RD_C2, 0, AL }, X+{"vsqrt.t", "?x2z,?s2y", 0xd0168000, 0xffff8080, RD_C2, 0, AL }, X+{"vasin.t", "?x2z,?s2y", 0xd0178000, 0xffff8080, RD_C2, 0, AL }, X+{"vnrcp.t", "?x2z,?s2y", 0xd0188000, 0xffff8080, RD_C2, 0, AL }, X+{"vnsin.t", "?x2z,?s2y", 0xd01a8000, 0xffff8080, RD_C2, 0, AL }, X+{"vrexp2.t", "?x2z,?s2y", 0xd01c8000, 0xffff8080, RD_C2, 0, AL }, X+{"vrndi.t", "?d2z", 0xd0218000, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf1.t", "?d2z", 0xd0228000, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf2.t", "?d2z", 0xd0238000, 0xffffff80, RD_C2, 0, AL }, X+{"vocp.t", "?d2d,?s2y", 0xd0448000, 0xffff8080, RD_C2, 0, AL }, X+{"vfad.t", "?d0d,?s2s", 0xd0468000, 0xffff8080, RD_C2, 0, AL }, X+{"vavg.t", "?d0d,?s2s", 0xd0478000, 0xffff8080, RD_C2, 0, AL }, X+{"vf2in.t", "?d2m,?s2s,?b", 0xd2008000, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iz.t", "?d2m,?s2s,?b", 0xd2208000, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iu.t", "?d2m,?s2s,?b", 0xd2408000, 0xffe08080, RD_C2, 0, AL }, X+{"vf2id.t", "?d2m,?s2s,?b", 0xd2608000, 0xffe08080, RD_C2, 0, AL }, X+{"vi2f.t", "?d2d,?s2w,?b", 0xd2808000, 0xffe08080, RD_C2, 0, AL }, X+{"vcmov.t", "?d2d,?s2s,?e", 0, (int) M_VCMOV_T, INSN_MACRO, 0, AL }, X+{"vcmovt.t", "?d2d,?s2s,?e", 0xd2a08000, 0xfff88080, RD_C2, 0, AL }, X+{"vcmovf.t", "?d2d,?s2s,?e", 0xd2a88000, 0xfff88080, RD_C2, 0, AL }, X+{"vmmul.t", "?v6z,?s6y,?t6x", 0xf0008000, 0xff808080, RD_C2, 0, AL }, X+{"vtfm3.t", "?v2z,?s6y,?t2x", 0xf1008000, 0xff808080, RD_C2, 0, AL }, X+{"vhtfm3.t", "?v2z,?s6y,?t2x", 0xf1000080, 0xff808080, RD_C2, 0, AL }, X+{"vmscl.t", "?x6z,?s6y,?t0x", 0xf2008000, 0xff808080, RD_C2, 0, AL }, X+{"vmmov.t", "?x6z,?s6y", 0xf3808000, 0xffff8080, RD_C2, 0, AL }, X+{"vmidt.t", "?d6z", 0xf3838000, 0xffffff80, RD_C2, 0, AL }, X+{"vmzero.t", "?d6z", 0xf3868000, 0xffffff80, RD_C2, 0, AL }, X+{"vmone.t", "?d6z", 0xf3878000, 0xffffff80, RD_C2, 0, AL }, X+{"vrot.t", "?x2z,?s0y,?w", 0xf3a08000, 0xffe08080, RD_C2, 0, AL }, X+{"vcrsp.t", "?d2z,?s2y,?t2x", 0xf2808000, 0xff808080, RD_C2, 0, AL }, X+{"vadd.p", "?d1d,?s1s,?t1t", 0x60000080, 0xff808080, RD_C2, 0, AL }, X+{"vsub.p", "?d1d,?s1s,?t1t", 0x60800080, 0xff808080, RD_C2, 0, AL }, X+{"vdiv.p", "?x1z,?s1y,?t1x", 0x63800080, 0xff808080, RD_C2, 0, AL }, X+{"vmul.p", "?d1d,?s1s,?t1t", 0x64000080, 0xff808080, RD_C2, 0, AL }, X+{"vdot.p", "?d0d,?s1s,?t1t", 0x64800080, 0xff808080, RD_C2, 0, AL }, X+{"vscl.p", "?d1d,?s1s,?t0x", 0x65000080, 0xff808080, RD_C2, 0, AL }, X+{"vhdp.p", "?d0d,?s1y,?t1t", 0x66000080, 0xff808080, RD_C2, 0, AL }, X+{"vdet.p", "?d0d,?s1s,?t1x", 0x67000080, 0xff808080, RD_C2, 0, AL }, X+{"vcmp.p", "?f2,?s1s,?t1t", 0x6c000080, 0xff8080f0, RD_C2, 0, AL }, X+{"vcmp.p", "?f1,?s1s", 0x6c000080, 0xffff80f0, RD_C2, 0, AL }, X+{"vcmp.p", "?f0", 0x6c000080, 0xfffffff0, RD_C2, 0, AL }, X+{"vmin.p", "?d1d,?s1s,?t1t", 0x6d000080, 0xff808080, RD_C2, 0, AL }, X+{"vmax.p", "?d1d,?s1s,?t1t", 0x6d800080, 0xff808080, RD_C2, 0, AL }, X+{"vsgn.p", "?d1d,?s1s", 0xd04a0080, 0xffff8080, RD_C2, 0, AL }, X+{"vcst.p", "?d1d,?a", 0xd0600080, 0xffe0ff80, RD_C2, 0, AL }, X+{"vscmp.p", "?d1d,?s1s,?t1t", 0x6e800080, 0xff808080, RD_C2, 0, AL }, X+{"vsge.p", "?d1d,?s1s,?t1t", 0x6f000080, 0xff808080, RD_C2, 0, AL }, X+{"vslt.p", "?d1d,?s1s,?t1t", 0x6f800080, 0xff808080, RD_C2, 0, AL }, X+{"vus2i.p", "?d3m,?s1y", 0xd03a0080, 0xffff8080, RD_C2, 0, AL }, X+{"vs2i.p", "?d3m,?s1y", 0xd03b0080, 0xffff8080, RD_C2, 0, AL }, X+{"vi2us.p", "?d0m,?s1w", 0xd03e0080, 0xffff8080, RD_C2, 0, AL }, X+{"vi2s.p", "?d0m,?s1w", 0xd03f0080, 0xffff8080, RD_C2, 0, AL }, X+{"vmov.p", "?d1d,?s1s", 0xd0000080, 0xffff8080, RD_C2, 0, AL }, X+{"vabs.p", "?d1d,?s1w", 0xd0010080, 0xffff8080, RD_C2, 0, AL }, X+{"vneg.p", "?d1d,?s1w", 0xd0020080, 0xffff8080, RD_C2, 0, AL }, X+{"vidt.p", "?d1d", 0xd0030080, 0xffffff80, RD_C2, 0, AL }, X+{"vsat0.p", "?d1z,?s1s", 0xd0040080, 0xffff8080, RD_C2, 0, AL }, X+{"vsat1.p", "?d1z,?s1s", 0xd0050080, 0xffff8080, RD_C2, 0, AL }, X+{"vzero.p", "?d1d", 0xd0060080, 0xffffff80, RD_C2, 0, AL }, X+{"vone.p", "?d1d", 0xd0070080, 0xffffff80, RD_C2, 0, AL }, X+{"vrcp.p", "?x1z,?s1y", 0xd0100080, 0xffff8080, RD_C2, 0, AL }, X+{"vrsq.p", "?x1z,?s1y", 0xd0110080, 0xffff8080, RD_C2, 0, AL }, X+{"vsin.p", "?x1z,?s1y", 0xd0120080, 0xffff8080, RD_C2, 0, AL }, X+{"vcos.p", "?x1z,?s1y", 0xd0130080, 0xffff8080, RD_C2, 0, AL }, X+{"vexp2.p", "?x1z,?s1y", 0xd0140080, 0xffff8080, RD_C2, 0, AL }, X+{"vlog2.p", "?x1z,?s1y", 0xd0150080, 0xffff8080, RD_C2, 0, AL }, X+{"vsqrt.p", "?x1z,?s1y", 0xd0160080, 0xffff8080, RD_C2, 0, AL }, X+{"vasin.p", "?x1z,?s1y", 0xd0170080, 0xffff8080, RD_C2, 0, AL }, X+{"vnrcp.p", "?x1z,?s1y", 0xd0180080, 0xffff8080, RD_C2, 0, AL }, X+{"vnsin.p", "?x1z,?s1y", 0xd01a0080, 0xffff8080, RD_C2, 0, AL }, X+{"vrexp2.p", "?x1z,?s1y", 0xd01c0080, 0xffff8080, RD_C2, 0, AL }, X+{"vrndi.p", "?d1z", 0xd0210080, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf1.p", "?d1z", 0xd0220080, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf2.p", "?d1z", 0xd0230080, 0xffffff80, RD_C2, 0, AL }, X+{"vf2h.p", "?d0m,?s1s", 0xd0320080, 0xffff8080, RD_C2, 0, AL }, X+{"vh2f.p", "?d3d,?s1y", 0xd0330080, 0xffff8080, RD_C2, 0, AL }, X+{"vbfy1.p", "?d1d,?s1s", 0xd0420080, 0xffff8080, RD_C2, 0, AL }, X+{"vocp.p", "?d1d,?s1y", 0xd0440080, 0xffff8080, RD_C2, 0, AL }, X+{"vsocp.p", "?d3z,?s1y", 0xd0450080, 0xffff8080, RD_C2, 0, AL }, X+{"vfad.p", "?d0d,?s1s", 0xd0460080, 0xffff8080, RD_C2, 0, AL }, X+{"vavg.p", "?d0d,?s1s", 0xd0470080, 0xffff8080, RD_C2, 0, AL }, X+{"vf2in.p", "?d1m,?s1s,?b", 0xd2000080, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iz.p", "?d1m,?s1s,?b", 0xd2200080, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iu.p", "?d1m,?s1s,?b", 0xd2400080, 0xffe08080, RD_C2, 0, AL }, X+{"vf2id.p", "?d1m,?s1s,?b", 0xd2600080, 0xffe08080, RD_C2, 0, AL }, X+{"vi2f.p", "?d1d,?s1w,?b", 0xd2800080, 0xffe08080, RD_C2, 0, AL }, X+{"vcmov.p", "?d1d,?s1s,?e", 0, (int) M_VCMOV_P, INSN_MACRO, 0, AL }, X+{"vcmovt.p", "?d1d,?s1s,?e", 0xd2a00080, 0xfff88080, RD_C2, 0, AL }, X+{"vcmovf.p", "?d1d,?s1s,?e", 0xd2a80080, 0xfff88080, RD_C2, 0, AL }, X+{"vmmul.p", "?v5z,?s5y,?t5x", 0xf0000080, 0xff808080, RD_C2, 0, AL }, X+{"vtfm2.p", "?v1z,?s5y,?t1x", 0xf0800080, 0xff808080, RD_C2, 0, AL }, X+{"vhtfm2.p", "?v1z,?s5y,?t1x", 0xf0800000, 0xff808080, RD_C2, 0, AL }, X+{"vmscl.p", "?x5z,?s5y,?t0x", 0xf2000080, 0xff808080, RD_C2, 0, AL }, X+{"vmmov.p", "?x5z,?s5y", 0xf3800080, 0xffff8080, RD_C2, 0, AL }, X+{"vmidt.p", "?d5z", 0xf3830080, 0xffffff80, RD_C2, 0, AL }, X+{"vmzero.p", "?d5z", 0xf3860080, 0xffffff80, RD_C2, 0, AL }, X+{"vmone.p", "?d5z", 0xf3870080, 0xffffff80, RD_C2, 0, AL }, X+{"vrot.p", "?x1z,?s0y,?w", 0xf3a00080, 0xffe08080, RD_C2, 0, AL }, X+{"vadd.s", "?d0d,?s0s,?t0t", 0x60000000, 0xff808080, RD_C2, 0, AL }, X+{"vsub.s", "?d0d,?s0s,?t0t", 0x60800000, 0xff808080, RD_C2, 0, AL }, X+{"vdiv.s", "?x0d,?s0s,?t0t", 0x63800000, 0xff808080, RD_C2, 0, AL }, X+{"vmul.s", "?d0d,?s0s,?t0t", 0x64000000, 0xff808080, RD_C2, 0, AL }, X+{"vcmp.s", "?f2,?s0s,?t0t", 0x6c000000, 0xff8080f0, RD_C2, 0, AL }, X+{"vcmp.s", "?f1,?s0s", 0x6c000000, 0xffff80f0, RD_C2, 0, AL }, X+{"vcmp.s", "?f0", 0x6c000000, 0xfffffff0, RD_C2, 0, AL }, X+{"vmin.s", "?d0d,?s0s,?t0t", 0x6d000000, 0xff808080, RD_C2, 0, AL }, X+{"vmax.s", "?d0d,?s0s,?t0t", 0x6d800000, 0xff808080, RD_C2, 0, AL }, X+{"vsgn.s", "?d0d,?s0s", 0xd04a0000, 0xffff8080, RD_C2, 0, AL }, X+{"vcst.s", "?d0d,?a", 0xd0600000, 0xffe0ff80, RD_C2, 0, AL }, X+{"vscmp.s", "?d0d,?s0s,?t0t", 0x6e800000, 0xff808080, RD_C2, 0, AL }, X+{"vsge.s", "?d0d,?s0s,?t0t", 0x6f000000, 0xff808080, RD_C2, 0, AL }, X+{"vslt.s", "?d0d,?s0s,?t0t", 0x6f800000, 0xff808080, RD_C2, 0, AL }, X+{"vus2i.s", "?d1m,?s0y", 0xd03a0000, 0xffff8080, RD_C2, 0, AL }, X+{"vs2i.s", "?d1m,?s0y", 0xd03b0000, 0xffff8080, RD_C2, 0, AL }, X+{"vmov.s", "?d0d,?s0s", 0xd0000000, 0xffff8080, RD_C2, 0, AL }, X+{"vabs.s", "?d0d,?s0w", 0xd0010000, 0xffff8080, RD_C2, 0, AL }, X+{"vneg.s", "?d0d,?s0w", 0xd0020000, 0xffff8080, RD_C2, 0, AL }, X+{"vsat0.s", "?d0z,?s0s", 0xd0040000, 0xffff8080, RD_C2, 0, AL }, X+{"vsat1.s", "?d0z,?s0s", 0xd0050000, 0xffff8080, RD_C2, 0, AL }, X+{"vzero.s", "?d0d", 0xd0060000, 0xffffff80, RD_C2, 0, AL }, X+{"vone.s", "?d0d", 0xd0070000, 0xffffff80, RD_C2, 0, AL }, X+{"vrcp.s", "?x0d,?s0s", 0xd0100000, 0xffff8080, RD_C2, 0, AL }, X+{"vrsq.s", "?x0d,?s0s", 0xd0110000, 0xffff8080, RD_C2, 0, AL }, X+{"vsin.s", "?x0d,?s0s", 0xd0120000, 0xffff8080, RD_C2, 0, AL }, X+{"vcos.s", "?x0d,?s0s", 0xd0130000, 0xffff8080, RD_C2, 0, AL }, X+{"vexp2.s", "?x0d,?s0s", 0xd0140000, 0xffff8080, RD_C2, 0, AL }, X+{"vlog2.s", "?x0d,?s0s", 0xd0150000, 0xffff8080, RD_C2, 0, AL }, X+{"vsqrt.s", "?x0d,?s0s", 0xd0160000, 0xffff8080, RD_C2, 0, AL }, X+{"vasin.s", "?x0d,?s0s", 0xd0170000, 0xffff8080, RD_C2, 0, AL }, X+{"vnrcp.s", "?x0d,?s0y", 0xd0180000, 0xffff8080, RD_C2, 0, AL }, X+{"vnsin.s", "?x0d,?s0y", 0xd01a0000, 0xffff8080, RD_C2, 0, AL }, X+{"vrexp2.s", "?x0d,?s0y", 0xd01c0000, 0xffff8080, RD_C2, 0, AL }, X+{"vrnds.s", "?s0y", 0xd0200000, 0xffff80ff, RD_C2, 0, AL }, X+{"vrndi.s", "?d0d", 0xd0210000, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf1.s", "?d0d", 0xd0220000, 0xffffff80, RD_C2, 0, AL }, X+{"vrndf2.s", "?d0d", 0xd0230000, 0xffffff80, RD_C2, 0, AL }, X+{"vh2f.s", "?d1d,?s0y", 0xd0330000, 0xffff8080, RD_C2, 0, AL }, X+{"vsbz.s", "?d0d,?s0s", 0xd0360000, 0xffff8080, RD_C2, 0, AL }, X+{"vsbn.s", "?d0d,?s0s,?t0t", 0x61000000, 0xff808080, RD_C2, 0, AL }, X+{"vlgb.s", "?d0d,?s0s", 0xd0370000, 0xffff8080, RD_C2, 0, AL }, X+{"vocp.s", "?d0d,?s0y", 0xd0440000, 0xffff8080, RD_C2, 0, AL }, X+{"vsocp.s", "?d1z,?s0y", 0xd0450000, 0xffff8080, RD_C2, 0, AL }, X+{"vf2in.s", "?d0m,?s0s,?b", 0xd2000000, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iz.s", "?d0m,?s0s,?b", 0xd2200000, 0xffe08080, RD_C2, 0, AL }, X+{"vf2iu.s", "?d0m,?s0s,?b", 0xd2400000, 0xffe08080, RD_C2, 0, AL }, X+{"vf2id.s", "?d0m,?s0s,?b", 0xd2600000, 0xffe08080, RD_C2, 0, AL }, X+{"vi2f.s", "?d0d,?s0w,?b", 0xd2800000, 0xffe08080, RD_C2, 0, AL }, X+{"vcmov.s", "?d0d,?s0s,?e", 0, (int) M_VCMOV_S, INSN_MACRO, 0, AL }, X+{"vcmovt.s", "?d0d,?s0s,?e", 0xd2a00000, 0xfff88080, RD_C2, 0, AL }, X+{"vcmovf.s", "?d0d,?s0s,?e", 0xd2a80000, 0xfff88080, RD_C2, 0, AL }, X+{"vwbn.s", "?d0d,?s0s,?i", 0xd3000000, 0xff008080, RD_C2, 0, AL }, X+{"vpfxs", "?0,?1,?2,?3", 0xdc000000, 0xff000000, RD_C2, 0, AL }, X+{"vpfxt", "?0,?1,?2,?3", 0xdd000000, 0xff000000, RD_C2, 0, AL }, X+{"vpfxd", "?4,?5,?6,?7", 0xde000000, 0xff000000, RD_C2, 0, AL }, X+{"viim.s", "?t0d,j", 0xdf000000, 0xff800000, RD_C2, 0, AL }, X+{"vfim.s", "?t0d,?u", 0xdf800000, 0xff800000, RD_C2, 0, AL }, X+{"vnop", "", 0xffff0000, 0xffffffff, RD_C2, 0, AL }, X+{"vflush", "", 0xffff040d, 0xffffffff, RD_C2, 0, AL }, X+{"vsync", "", 0xffff0320, 0xffffffff, RD_C2, 0, AL }, X+{"vsync", "i", 0xffff0000, 0xffff0000, RD_C2, 0, AL }, X+ X /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format X instructions so they are here for the latters to take precedence. */ X {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, X@@ -1198,6 +1505,36 @@ X {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, X {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, X X+/* Coprocessor 2 load/store operations overlap with the Allegrex VFPU X+ instructions so they are here for the latters to take precedence. */ X+/* COP1 ldc1 and sdc1 and COP3 ldc3 and sdc3 also overlap with the VFPU. */ X+{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, X+{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, X+{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, X+{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, X+{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ X+{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, X+{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, X+{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, X+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, X+{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, X+{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, X+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, X+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, X+{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, X+{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, X+{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, X+{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, X+{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, X+{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, X+{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, X+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, X+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, X+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, X+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, X+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, X+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, X+ X /* No hazard protection on coprocessor instructions--they shouldn't X change the state of the processor and if they do it's up to the X user to put in nops as necessary. These are at the end so that the END-of-psptoolchain-binutils/files/patch-opcodes-mips-opc.c echo x - psptoolchain-binutils/files/patch-opcodes-configure sed 's/^X//' >psptoolchain-binutils/files/patch-opcodes-configure << 'END-of-psptoolchain-binutils/files/patch-opcodes-configure' X--- opcodes/configure.orig 2009-02-26 14:47:03.000000000 +0100 X+++ opcodes/configure 2009-02-26 14:47:35.000000000 +0100 X@@ -4345,8 +4345,8 @@ X bfdlibdir='$(libdir)' X bfdincludedir='$(includedir)' X if test "${host}" != "${target}"; then X- bfdlibdir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/lib' X- bfdincludedir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/include' X+ bfdlibdir='$(exec_prefix)/$(target_noncanonical)/lib' X+ bfdincludedir='$(exec_prefix)/$(target_noncanonical)/include' X fi X X END-of-psptoolchain-binutils/files/patch-opcodes-configure echo x - psptoolchain-binutils/pkg-plist sed 's/^X//' >psptoolchain-binutils/pkg-plist << 'END-of-psptoolchain-binutils/pkg-plist' Xpsp/lib/libopcodes.la Xpsp/lib/libopcodes.a Xpsp/lib/libbfd.la Xpsp/lib/libbfd.a Xpsp/lib/ldscripts/elf_mipsallegrexel_psp.xu Xpsp/lib/ldscripts/elf_mipsallegrexel_psp.xs Xpsp/lib/ldscripts/elf_mipsallegrexel_psp.xr Xpsp/lib/ldscripts/elf_mipsallegrexel_psp.xn Xpsp/lib/ldscripts/elf_mipsallegrexel_psp.xbn Xpsp/lib/ldscripts/elf_mipsallegrexel_psp.x Xpsp/lib/ldscripts/elf32elmip.xw Xpsp/lib/ldscripts/elf32elmip.xu Xpsp/lib/ldscripts/elf32elmip.xsw Xpsp/lib/ldscripts/elf32elmip.xsc Xpsp/lib/ldscripts/elf32elmip.xs Xpsp/lib/ldscripts/elf32elmip.xr Xpsp/lib/ldscripts/elf32elmip.xn Xpsp/lib/ldscripts/elf32elmip.xc Xpsp/lib/ldscripts/elf32elmip.xbn Xpsp/lib/ldscripts/elf32elmip.x Xpsp/include/symcat.h Xpsp/include/dis-asm.h Xpsp/include/bfdlink.h Xpsp/include/bfd.h Xpsp/include/ansidecl.h Xpsp/bin/strip Xpsp/bin/ranlib Xpsp/bin/objdump Xpsp/bin/nm Xpsp/bin/ld Xpsp/bin/as Xpsp/bin/ar Xlib/libiberty.a Xbin/psp-strip Xbin/psp-strings Xbin/psp-size Xbin/psp-readelf Xbin/psp-ranlib Xbin/psp-objdump Xbin/psp-objcopy Xbin/psp-nm Xbin/psp-ld Xbin/psp-gprof Xbin/psp-c++filt Xbin/psp-as Xbin/psp-ar Xbin/psp-addr2line X@dirrm psp/lib/ldscripts X@dirrm psp/lib X@dirrm psp/include X@dirrm psp/bin X@dirrm psp END-of-psptoolchain-binutils/pkg-plist exit --- psptoolchain-binutils.shar ends here --- >Release-Note: >Audit-Trail: >Unformatted:
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