From owner-cvs-all@FreeBSD.ORG Wed Dec 6 12:50:24 2006 Return-Path: X-Original-To: cvs-all@FreeBSD.org Delivered-To: cvs-all@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 8596316A513; Wed, 6 Dec 2006 12:50:24 +0000 (UTC) (envelope-from bde@zeta.org.au) Received: from mailout1.pacific.net.au (mailout1-3.pacific.net.au [61.8.2.210]) by mx1.FreeBSD.org (Postfix) with ESMTP id CD5BF43E79; Wed, 6 Dec 2006 12:48:55 +0000 (GMT) (envelope-from bde@zeta.org.au) Received: from mailproxy2.pacific.net.au (mailproxy2.pacific.net.au [61.8.2.163]) by mailout1.pacific.net.au (Postfix) with ESMTP id 13E775A1D36; Wed, 6 Dec 2006 23:49:31 +1100 (EST) Received: from katana.zip.com.au (katana.zip.com.au [61.8.7.246]) by mailproxy2.pacific.net.au (Postfix) with ESMTP id 0E36B27404; Wed, 6 Dec 2006 23:49:29 +1100 (EST) Date: Wed, 6 Dec 2006 23:49:29 +1100 (EST) From: Bruce Evans X-X-Sender: bde@delplex.bde.org To: Suleiman Souhlal In-Reply-To: <45767A96.6070508@FreeBSD.org> Message-ID: <20061206233934.E33574@delplex.bde.org> References: <200612030349.kB33nTDO057097@repoman.freebsd.org> <45767A96.6070508@FreeBSD.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: Bruce Evans , cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/i386/isa clock.c src/sys/amd64/isa clock.c X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Dec 2006 12:50:24 -0000 On Wed, 6 Dec 2006, Suleiman Souhlal wrote: > Bruce Evans wrote: >> bde 2006-12-03 03:49:28 UTC >> >> FreeBSD src repository >> >> Modified files: >> sys/i386/isa clock.c sys/amd64/isa clock.c Log: >> Optimized RTC accesses by avoiding null writes to the index register >> and by only delaying when an RTC register is written to. The delay >> ... >> Optimizing RTC interrupt handling is more interesting than it used to >> be because RTC interrupts are currently needed to fix the more efficient >> apic timer interrupts on some systems. apic_timer_hz is normally 2000 >> so the RTC interrupt rate needs to be 2048 to keep the apic timer >> firing on such systems. ... > Why do we have both RTC and LAPIC timer interrupts at once? > Also, why does having the RTC interrupt rate being the same as the LAPIC > timers' > prevent the latter from firing? We don't in -current, but using another source of interrupts is the only known way to make lapic timer interrupts work when cpu_idle() stops apci timer interrupts. Having the RTC (or some other) interrupt rate larger than lapic timer rate makes the latter fire too (I think it fires aperiodically when the other interrupt wakes it up iff it was asleep). Bruce