From owner-svn-src-all@freebsd.org Wed Sep 23 01:56:27 2020 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 79D5D3E90F7; Wed, 23 Sep 2020 01:56:27 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Bx1Vz1gXGz44tX; Wed, 23 Sep 2020 01:56:27 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id BC9839206; Wed, 23 Sep 2020 01:56:26 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 08N1uQiN085235; Wed, 23 Sep 2020 01:56:26 GMT (envelope-from bdragon@FreeBSD.org) Received: (from bdragon@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 08N1uQeb085234; Wed, 23 Sep 2020 01:56:26 GMT (envelope-from bdragon@FreeBSD.org) Message-Id: <202009230156.08N1uQeb085234@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: bdragon set sender to bdragon@FreeBSD.org using -f From: Brandon Bergren Date: Wed, 23 Sep 2020 01:56:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r366053 - in head/sys/powerpc: aim include X-SVN-Group: head X-SVN-Commit-Author: bdragon X-SVN-Commit-Paths: in head/sys/powerpc: aim include X-SVN-Commit-Revision: 366053 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Sep 2020 01:56:29 -0000 Author: bdragon Date: Wed Sep 23 01:56:26 2020 New Revision: 366053 URL: https://svnweb.freebsd.org/changeset/base/366053 Log: [PowerPC64LE] Fix AP spinup on powernv. OPAL unconditionally enters secondary CPUs with only HV and SF set. I tried writing a secondary entry point instead, but OPAL rejected it and I am unsure why, so I resorted to making the system reset interrupt endian-flexible. This means we take a slight performance hit on wakeup on LE, but it is a good stopgap until we can figure out a reliable way to make OPAL enter where we want it to. It probably makes sense to have it around anyway, because I can imagine scenarios where the cpu resets itself to BE and does a software reset. Sponsored by: Tag1 Consulting, Inc. Modified: head/sys/powerpc/aim/trap_subr64.S head/sys/powerpc/include/asm.h Modified: head/sys/powerpc/aim/trap_subr64.S ============================================================================== --- head/sys/powerpc/aim/trap_subr64.S Wed Sep 23 01:56:21 2020 (r366052) +++ head/sys/powerpc/aim/trap_subr64.S Wed Sep 23 01:56:26 2020 (r366053) @@ -319,6 +319,19 @@ dtrace_invop_calltrap_addr: .globl CNAME(cpu_wakeup_handler) .p2align 3 CNAME(rstcode): +#ifdef __LITTLE_ENDIAN__ + /* + * XXX This shouldn't be necessary. + * + * According to the ISA documentation, LE should be set from HILE + * or the LPCR ILE bit automatically. However, the entry into this + * vector from OPAL_START_CPU does not honor this correctly. + * + * We should be able to define an alternate entry for opal's + * start_kernel_secondary asm code to branch to. + */ + RETURN_TO_NATIVE_ENDIAN +#endif /* * Check if this is software reset or * processor is waking up from power saving mode Modified: head/sys/powerpc/include/asm.h ============================================================================== --- head/sys/powerpc/include/asm.h Wed Sep 23 01:56:21 2020 (r366052) +++ head/sys/powerpc/include/asm.h Wed Sep 23 01:56:26 2020 (r366053) @@ -213,6 +213,9 @@ name: \ * wrong endian. * * This sequence is NMI-reentrant. + * + * Do not change the length of this sequence without looking at the users, + * this is used in size-constrained places like the reset vector! */ #define RETURN_TO_NATIVE_ENDIAN \ tdi 0, %r0, 0x48; /* Endian swapped: b . + 8 */\