Date: Thu, 22 Aug 2002 17:24:41 +0100 (BST) From: Bruce M Simpson <bms@spc.org> To: FreeBSD-gnats-submit@FreeBSD.org Subject: ports/41905: New port: sysutils/sjog Message-ID: <20020822162441.ECCAA9638@triage.dollah.com>
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>Number: 41905
>Category: ports
>Synopsis: New port: sysutils/sjog
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-ports
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: change-request
>Submitter-Id: current-users
>Arrival-Date: Thu Aug 22 09:30:01 PDT 2002
>Closed-Date:
>Last-Modified:
>Originator: Bruce M Simpson
>Release: FreeBSD 4.6-STABLE i386
>Organization:
>Environment:
System: FreeBSD triage.dollah.com 4.6-STABLE FreeBSD 4.6-STABLE #0: Tue Aug 20 13:00:06 BST 2002 root@triage.dollah.com:/usr/src/sys/compile/TRIAGE i386
>Description:
Program providing additional support for the Sony Vaio and Picturebook
jog dial interface device.
>How-To-Repeat:
>Fix:
--- sjog.shar begins here ---
# This is a shell archive. Save it in a file, remove anything before
# this line, and then unpack it by entering "sh file". Note, it may
# create directories; files and directories will be owned by you and
# have default permissions.
#
# This archive contains:
#
# sjog
# sjog/files
# sjog/files/patch-setbrightness::setbrightness.c
# sjog/files/patch-src::pci.h
# sjog/files/patch-src::pci_freebsd.c
# sjog/files/patch-src::sjog.c
# sjog/files/patch-src::sjog_spic.c
# sjog/files/patch-src::sjog_volume.c
# sjog/files/patch-src::sonypi.c
# sjog/files/patch-src::sonypi.h
# sjog/files/patch-setbrightness::Makefile.am
# sjog/files/patch-src::Makefile.am
# sjog/distinfo
# sjog/Makefile
# sjog/pkg-plist
# sjog/pkg-comment
# sjog/pkg-descr
#
echo c - sjog
mkdir -p sjog > /dev/null 2>&1
echo c - sjog/files
mkdir -p sjog/files > /dev/null 2>&1
echo x - sjog/files/patch-setbrightness::setbrightness.c
sed 's/^X//' >sjog/files/patch-setbrightness::setbrightness.c << 'END-of-sjog/files/patch-setbrightness::setbrightness.c'
X--- setbrightness/setbrightness.c.orig Sat Jul 28 18:16:22 2001
X+++ setbrightness/setbrightness.c Sat Aug 17 20:38:56 2002
X@@ -1,44 +1,58 @@
X+/* FreeBSD modifications by Jay Kuri jk@oneway.com 08/13/01 */
X+
X #define _XOPEN_SOURCE 500
X #include <stdio.h>
X #include <stdlib.h>
X #include <unistd.h>
X #include <fcntl.h>
X #include <errno.h>
X+#ifndef __FreeBSD__
X #include <sys/io.h>
X+#endif
X #include <sys/mman.h>
X #include <dirent.h>
X #include <ctype.h>
X #include <malloc.h>
X #include <string.h>
X #include <signal.h>
X+#ifndef __FreeBSD__
X #include <getopt.h>
X #include <linux/pci.h>
X+#endif
X #include <sys/time.h>
X+#ifdef __FreeBSD__
X+#include <machine/cpufunc.h>
X+#include "../src/sonypi.h"
X+#endif
X
X
X #define BRIGHTNESS 0x96
X #define DATA_REG 0x62
X #define CST_REG 0x66
X
X+#ifndef __FreeBSD__
X typedef unsigned short u16;
X+#define OUTW outw
X+#define OUTB outb
X+#endif
X
X static void ecr_set(u16 value)
X {
X while (inw(CST_REG) & 3) usleep(1);
X- outw(0x81, CST_REG);
X+ OUTW(0x81, CST_REG);
X while (inw(CST_REG) & 2) usleep(1);
X- outw(BRIGHTNESS, DATA_REG);
X+ OUTW(BRIGHTNESS, DATA_REG);
X while (inw(CST_REG) & 2) usleep(1);
X- outw(value, DATA_REG);
X+ OUTW(value, DATA_REG);
X while (inw(CST_REG) & 2) usleep(1);
X }
X
X static u16 ecr_get()
X {
X while (inw(CST_REG) & 3) usleep(1);
X- outb(0x80, CST_REG);
X+ OUTB(0x80, CST_REG);
X while (inw(CST_REG) & 2) usleep(1);
X- outb(BRIGHTNESS, DATA_REG);
X+ OUTB(BRIGHTNESS, DATA_REG);
X while (inw(CST_REG) & 2) usleep(1);
X return (inw(DATA_REG)&255);
X }
X@@ -52,14 +66,17 @@
X int main(int argc, char *argv[])
X {
X
X+#ifndef __FreeBSD__
X ioperm(DATA_REG, 0x08, 1);
X+#endif
X if( geteuid() != 0 )
X fprintf(stdout, "You must be root to use %s\n", argv[0]);
X
X else if( argc == 2 && strcmp(argv[1], "--read") == 0)
X+ {
X+ iopl(3);
X printf("%d\n", ecr_get());
X-
X- else if( argc != 2 || !isdigit(argv[1][0]))
X+ } else if( argc != 2 || !isdigit(argv[1][0]))
X usage();
X
X else
END-of-sjog/files/patch-setbrightness::setbrightness.c
echo x - sjog/files/patch-src::pci.h
sed 's/^X//' >sjog/files/patch-src::pci.h << 'END-of-sjog/files/patch-src::pci.h'
X--- src/pci.h.orig Sat Aug 17 20:38:56 2002
X+++ src/pci.h Sat Aug 17 20:38:56 2002
X@@ -0,0 +1,275 @@
X+/*
X+ * $Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
X+ *
X+ * PCI defines and function prototypes
X+ * Copyright 1994, Drew Eckhardt
X+ * Copyright 1997--1999 Martin Mares <mj@suse.cz>
X+ *
X+ * For more information, please consult the following manuals (look at
X+ * http://www.pcisig.com/ for how to get them):
X+ *
X+ * PCI BIOS Specification
X+ * PCI Local Bus Specification
X+ * PCI to PCI Bridge Specification
X+ * PCI System Design Guide
X+ */
X+
X+#ifndef LINUX_PCI_H
X+#define LINUX_PCI_H
X+
X+/*
X+ * Under PCI, each device has 256 bytes of configuration address space,
X+ * of which the first 64 bytes are standardized as follows:
X+ */
X+#define PCI_VENDOR_ID 0x00 /* 16 bits */
X+#define PCI_DEVICE_ID 0x02 /* 16 bits */
X+#define PCI_COMMAND 0x04 /* 16 bits */
X+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
X+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
X+#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
X+#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
X+#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
X+#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
X+#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
X+#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
X+#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
X+#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
X+
X+#define PCI_STATUS 0x06 /* 16 bits */
X+#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
X+#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
X+#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
X+#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
X+#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
X+#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
X+#define PCI_STATUS_DEVSEL_FAST 0x000
X+#define PCI_STATUS_DEVSEL_MEDIUM 0x200
X+#define PCI_STATUS_DEVSEL_SLOW 0x400
X+#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
X+#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
X+#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
X+#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
X+#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
X+
X+#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
X+ revision */
X+#define PCI_REVISION_ID 0x08 /* Revision ID */
X+#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
X+#define PCI_CLASS_DEVICE 0x0a /* Device class */
X+
X+#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
X+#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
X+#define PCI_HEADER_TYPE 0x0e /* 8 bits */
X+#define PCI_HEADER_TYPE_NORMAL 0
X+#define PCI_HEADER_TYPE_BRIDGE 1
X+#define PCI_HEADER_TYPE_CARDBUS 2
X+
X+#define PCI_BIST 0x0f /* 8 bits */
X+#define PCI_BIST_CODE_MASK 0x0f /* Return result */
X+#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
X+#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
X+
X+/*
X+ * Base addresses specify locations in memory or I/O space.
X+ * Decoded size can be determined by writing a value of
X+ * 0xffffffff to the register, and reading it back. Only
X+ * 1 bits are decoded.
X+ */
X+#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
X+#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
X+#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
X+#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
X+#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
X+#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
X+#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
X+#define PCI_BASE_ADDRESS_SPACE_IO 0x01
X+#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
X+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
X+#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
X+#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
X+#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
X+#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
X+#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
X+#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
X+/* bit 1 is reserved if address_space = 1 */
X+
X+/* Header type 0 (normal devices) */
X+#define PCI_CARDBUS_CIS 0x28
X+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
X+#define PCI_SUBSYSTEM_ID 0x2e
X+#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
X+#define PCI_ROM_ADDRESS_ENABLE 0x01
X+#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
X+
X+#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
X+
X+/* 0x35-0x3b are reserved */
X+#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
X+#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
X+#define PCI_MIN_GNT 0x3e /* 8 bits */
X+#define PCI_MAX_LAT 0x3f /* 8 bits */
X+
X+/* Header type 1 (PCI-to-PCI bridges) */
X+#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
X+#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
X+#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
X+#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
X+#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
X+#define PCI_IO_LIMIT 0x1d
X+#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
X+#define PCI_IO_RANGE_TYPE_16 0x00
X+#define PCI_IO_RANGE_TYPE_32 0x01
X+#define PCI_IO_RANGE_MASK ~0x0f
X+#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
X+#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
X+#define PCI_MEMORY_LIMIT 0x22
X+#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
X+#define PCI_MEMORY_RANGE_MASK ~0x0f
X+#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
X+#define PCI_PREF_MEMORY_LIMIT 0x26
X+#define PCI_PREF_RANGE_TYPE_MASK 0x0f
X+#define PCI_PREF_RANGE_TYPE_32 0x00
X+#define PCI_PREF_RANGE_TYPE_64 0x01
X+#define PCI_PREF_RANGE_MASK ~0x0f
X+#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
X+#define PCI_PREF_LIMIT_UPPER32 0x2c
X+#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
X+#define PCI_IO_LIMIT_UPPER16 0x32
X+/* 0x34 same as for htype 0 */
X+/* 0x35-0x3b is reserved */
X+#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
X+/* 0x3c-0x3d are same as for htype 0 */
X+#define PCI_BRIDGE_CONTROL 0x3e
X+#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
X+#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
X+#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
X+#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
X+#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
X+#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
X+#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
X+
X+/* Header type 2 (CardBus bridges) */
X+/* 0x14-0x15 reserved */
X+#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
X+#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
X+#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
X+#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
X+#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
X+#define PCI_CB_MEMORY_BASE_0 0x1c
X+#define PCI_CB_MEMORY_LIMIT_0 0x20
X+#define PCI_CB_MEMORY_BASE_1 0x24
X+#define PCI_CB_MEMORY_LIMIT_1 0x28
X+#define PCI_CB_IO_BASE_0 0x2c
X+#define PCI_CB_IO_BASE_0_HI 0x2e
X+#define PCI_CB_IO_LIMIT_0 0x30
X+#define PCI_CB_IO_LIMIT_0_HI 0x32
X+#define PCI_CB_IO_BASE_1 0x34
X+#define PCI_CB_IO_BASE_1_HI 0x36
X+#define PCI_CB_IO_LIMIT_1 0x38
X+#define PCI_CB_IO_LIMIT_1_HI 0x3a
X+#define PCI_CB_IO_RANGE_MASK ~0x03
X+/* 0x3c-0x3d are same as for htype 0 */
X+#define PCI_CB_BRIDGE_CONTROL 0x3e
X+#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
X+#define PCI_CB_BRIDGE_CTL_SERR 0x02
X+#define PCI_CB_BRIDGE_CTL_ISA 0x04
X+#define PCI_CB_BRIDGE_CTL_VGA 0x08
X+#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
X+#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
X+#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
X+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
X+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
X+#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
X+#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
X+#define PCI_CB_SUBSYSTEM_ID 0x42
X+#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
X+/* 0x48-0x7f reserved */
X+
X+/* Capability lists */
X+
X+#define PCI_CAP_LIST_ID 0 /* Capability ID */
X+#define PCI_CAP_ID_PM 0x01 /* Power Management */
X+#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
X+#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
X+#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
X+#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
X+#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
X+#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
X+#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
X+#define PCI_CAP_SIZEOF 4
X+
X+/* Power Management Registers */
X+
X+#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
X+#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
X+#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
X+#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
X+#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
X+#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
X+#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
X+#define PCI_PM_CTRL 4 /* PM control and status register */
X+#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
X+#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
X+#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
X+#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
X+#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
X+#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
X+#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
X+#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
X+#define PCI_PM_DATA_REGISTER 7 /* (??) */
X+#define PCI_PM_SIZEOF 8
X+
X+/* AGP registers */
X+
X+#define PCI_AGP_VERSION 2 /* BCD version number */
X+#define PCI_AGP_RFU 3 /* Rest of capability flags */
X+#define PCI_AGP_STATUS 4 /* Status register */
X+#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
X+#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
X+#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
X+#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
X+#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
X+#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
X+#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
X+#define PCI_AGP_COMMAND 8 /* Control register */
X+#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
X+#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
X+#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
X+#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
X+#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
X+#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
X+#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
X+#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
X+#define PCI_AGP_SIZEOF 12
X+
X+/* Slot Identification */
X+
X+#define PCI_SID_ESR 2 /* Expansion Slot Register */
X+#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
X+#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
X+#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
X+
X+/* Message Signalled Interrupts registers */
X+
X+#define PCI_MSI_FLAGS 2 /* Various flags */
X+#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
X+#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
X+#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
X+#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
X+#define PCI_MSI_RFU 3 /* Rest of capability flags */
X+#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
X+#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
X+#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
X+#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
X+
X+int pci_find_device(u32 vendor, u32 device);
X+int pci_config_write_u8(int fd, int ofs, u8 v);
X+int pci_config_write_u16(int fd, int ofs, u16 v);
X+int pci_config_write_u32(int fd, int ofs, u32 v);
X+int pci_config_read_u8(int fd, int ofs, u8 *v);
X+int pci_config_read_u16(int fd, int ofs, u16 *v);
X+int pci_config_read_u32(int fd, int ofs, u32 *v);
X+u32 pci_read_base_address(u32 vendor, u32 device);
X+
X+#endif
X+
END-of-sjog/files/patch-src::pci.h
echo x - sjog/files/patch-src::pci_freebsd.c
sed 's/^X//' >sjog/files/patch-src::pci_freebsd.c << 'END-of-sjog/files/patch-src::pci_freebsd.c'
X--- src/pci_freebsd.c.orig Sat Aug 17 20:38:56 2002
X+++ src/pci_freebsd.c Sat Aug 17 20:38:56 2002
X@@ -0,0 +1,150 @@
X+/* manipulate PCI devices from user space
X+
X+ Tridge, July 2000
X+
X+ FreeBSD modifications for sjog by Jay Kuri jk@oneway.com 08/13/01
X+*/
X+/*
X+ Copyright (C) Andrew Tridgell 2000
X+ Copyright (C) Takanori Watanabe 2000
X+
X+ This program is free software; you can redistribute it and/or modify
X+ it under the terms of the GNU General Public License as published by
X+ the Free Software Foundation; either version 2 of the License, or
X+ (at your option) any later version.
X+
X+ This program is distributed in the hope that it will be useful,
X+ but WITHOUT ANY WARRANTY; without even the implied warranty of
X+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
X+ GNU General Public License for more details.
X+
X+ You should have received a copy of the GNU General Public License
X+ along with this program; if not, write to the Free Software
X+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
X+*/
X+#include <sys/types.h>
X+#include <sys/pciio.h>
X+#include <sys/fcntl.h>
X+#include "sonypi.h"
X+#define MAX_BUS 8
X+
X+#define PCI_GETCONF_MATCH_VENDDEV (PCI_GETCONF_MATCH_VENDOR|PCI_GETCONF_MATCH_DEVICE)
X+#define MAXHANDLE 32
X+
X+static struct pci_io pio[MAXHANDLE];
X+static u_int32_t handlebmp=0;
X+static int pci_fd=-1;
X+static int pcifd_internal_init();
X+int pcifd_internal_init()
X+{
X+ return pci_fd=open("/dev/pci",O_RDWR,0);
X+}
X+/* find a PCI device and return a handle to it */
X+int pci_find_device(u32 vendor, u32 device)
X+{
X+
X+ struct pci_conf pc[4];/*I think only one is enough*/
X+ struct pci_conf_io pcfi;
X+ struct pci_match_conf pmc={{0,0,0},"",0,0xffff,0xffff,0,
X+ PCI_GETCONF_MATCH_VENDDEV};
X+ int handle;
X+ if(pci_fd==-1){
X+ if(pcifd_internal_init()==-1)
X+ return -1;
X+ }
X+ pmc.pc_vendor=vendor;
X+ pmc.pc_device=device;
X+ pcfi.pat_buf_len=sizeof(pmc);
X+ pcfi.num_patterns=1;
X+ pcfi.patterns=&pmc;
X+ pcfi.match_buf_len=sizeof(pc);
X+ pcfi.num_matches=0;
X+ pcfi.matches=pc;
X+ pcfi.offset=0;
X+ pcfi.generation=0;
X+ ioctl(pci_fd,PCIOCGETCONF,&pcfi);
X+ if(pcfi.num_matches==0){
X+ goto error;
X+ }
X+ for(handle=0;handle<32;handle++){
X+ if(!(handlebmp&(1<<handle))){
X+ pio[handle].pi_sel=pc[0].pc_sel;
X+ handlebmp|=(1<<handle);
X+ return handle;
X+ }
X+ }
X+ error:
X+ close(pci_fd);
X+ return -1;
X+}
X+
X+
X+/* routines to read and write PCI config space */
X+#define PCICFGWACCESSOR(bsize) \
X+int pci_config_write_u##bsize(int fd, int ofs, u##bsize v)\
X+{\
X+ int result;\
X+ if(fd==-1){\
X+ return -1;\
X+ }\
X+ if(pci_fd==-1){\
X+ if(pcifd_internal_init()==-1)\
X+ return -1;\
X+ }\
X+ pio[fd].pi_reg=ofs;\
X+ pio[fd].pi_width=bsize/8;\
X+ pio[fd].pi_data=v;\
X+ result=ioctl(pci_fd,PCIOCWRITE,&pio[fd]);\
X+ return result;\
X+}
X+PCICFGWACCESSOR(8)
X+PCICFGWACCESSOR(16)
X+PCICFGWACCESSOR(32)
X+#undef PCICFGWACCESSOR
X+/*Acctually define
X+ pci_config_write_u8();
X+ pci_config_write_u16();
X+ pci_config_write_u32();
X+*/
X+#define PCICFGRACCESSOR(bsize) \
X+int pci_config_read_u##bsize(int fd, int ofs, u##bsize *v)\
X+{\
X+ int result;\
X+ if(fd==-1){\
X+ return -1;\
X+ }\
X+ if(pci_fd==-1){\
X+ if(pcifd_internal_init()==-1)\
X+ return -1;\
X+ }\
X+ pio[fd].pi_reg=ofs;\
X+ pio[fd].pi_width=bsize/8;\
X+ result=ioctl(pci_fd,PCIOCREAD,&pio[fd]);\
X+ *v=pio[fd].pi_data&((bsize==32)? 0xffffffff: (1<<bsize)-1);\
X+ return result;\
X+}
X+/*Acctually define
X+ pci_config_read_u8();
X+ pci_config_read_u16();
X+ pci_config_read_u32();
X+*/
X+PCICFGRACCESSOR(8)
X+PCICFGRACCESSOR(16)
X+PCICFGRACCESSOR(32)
X+#undef PCICFGRACCESSOR
X+
X+/* find a pci base address via /proc/bus/pci/devices. This seems to be
X+ needed on some boxes. Why? */
X+u_int32_t pci_read_base_address(u32 vendor, u32 device)
X+{
X+ return 0;/* In FreeBSD???*/
X+}
X+
X+
X+
X+
X+
X+
X+
X+
X+
END-of-sjog/files/patch-src::pci_freebsd.c
echo x - sjog/files/patch-src::sjog.c
sed 's/^X//' >sjog/files/patch-src::sjog.c << 'END-of-sjog/files/patch-src::sjog.c'
X--- src/sjog.c.orig Mon Aug 13 20:52:02 2001
X+++ src/sjog.c Sat Aug 17 20:38:56 2002
X@@ -10,7 +10,11 @@
X /* -------------------------------------------------------------------------- */
X
X gboolean reverseBrightness = TRUE;
X+#ifdef __FreeBSD__
X+gboolean useSpic = TRUE;
X+#else
X gboolean useSpic = FALSE;
X+#endif
X gboolean mousewheelFakeKeys = FALSE;
X gboolean centerWindow = TRUE;
X
END-of-sjog/files/patch-src::sjog.c
echo x - sjog/files/patch-src::sjog_spic.c
sed 's/^X//' >sjog/files/patch-src::sjog_spic.c << 'END-of-sjog/files/patch-src::sjog_spic.c'
X--- src/sjog_spic.c.orig Mon Aug 6 13:38:14 2001
X+++ src/sjog_spic.c Sat Aug 17 20:38:56 2002
X@@ -1,9 +1,17 @@
X+/* FreeBSD modifications by Jay Kuri jk@oneway.com 08/13/01 */
X+
X #include "sjog_spic.h"
X+#ifdef __FreeBSD__
X+#include "sonypi.h"
X+#endif
X
X void
X sjog_spic_init()
X {
X
X+#ifdef __FreeBSD__
X+ spic_init();
X+#else
X /* open spic device */
X if ((spic_fd = open(SPIC_DEVICE, O_RDONLY)) < 0)
X {
X@@ -11,6 +19,7 @@
X SPIC_DEVICE);
X exit(1);
X }
X+#endif
X
X }
X
X@@ -24,12 +33,16 @@
X fprintf(stdout, "sjog_spic_read_jog: spic_fd=%d\n", spic_fd);
X #endif
X
X+#ifdef __FreeBSD__
X+ jog = spic_jogger_turned();
X+#else
X if (read(spic_fd, (gchar *) & jog, sizeof(gint)) < 0)
X {
X fprintf(stderr, "%s read error!\n", SPIC_DEVICE);
X close(spic_fd);
X exit(1);
X }
X+#endif
X
X sjog_jog_position_changed(jog);
X
END-of-sjog/files/patch-src::sjog_spic.c
echo x - sjog/files/patch-src::sjog_volume.c
sed 's/^X//' >sjog/files/patch-src::sjog_volume.c << 'END-of-sjog/files/patch-src::sjog_volume.c'
X--- src/sjog_volume.c.orig Sun Aug 12 23:17:33 2001
X+++ src/sjog_volume.c Sat Aug 17 20:38:56 2002
X@@ -1,5 +1,9 @@
X #include <sys/ioctl.h>
X+#ifdef __FreeBSD__
X+#include <machine/soundcard.h>
X+#else
X #include <linux/soundcard.h>
X+#endif
X
X #include "sjog.h"
X #include "sjog_volume.h"
END-of-sjog/files/patch-src::sjog_volume.c
echo x - sjog/files/patch-src::sonypi.c
sed 's/^X//' >sjog/files/patch-src::sonypi.c << 'END-of-sjog/files/patch-src::sonypi.c'
X--- src/sonypi.c.orig Sat Aug 17 20:38:56 2002
X+++ src/sonypi.c Sat Aug 17 20:38:56 2002
X@@ -0,0 +1,431 @@
X+/* sony programmable I/O control device (SPIC) functions for picturebook
X+
X+ Tridge and sfr, July 2000
X+
X+ FreeBSD modifications by Jay Kuri jk@oneway.com 08/13/01
X+*/
X+/*
X+ Copyright (C) Andrew Tridgell 2000
X+
X+ This program is free software; you can redistribute it and/or modify
X+ it under the terms of the GNU General Public License as published by
X+ the Free Software Foundation; either version 2 of the License, or
X+ (at your option) any later version.
X+
X+ This program is distributed in the hope that it will be useful,
X+ but WITHOUT ANY WARRANTY; without even the implied warranty of
X+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
X+ GNU General Public License for more details.
X+
X+ You should have received a copy of the GNU General Public License
X+ along with this program; if not, write to the Free Software
X+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
X+*/
X+
X+
X+#include "sonypi.h"
X+#include "pci.h"
X+
X+static int spic_fd;
X+static int debug=0;
X+#ifdef LINUX
X+static void OUTB(u8 v, int port)
X+{
X+ outb(v, port);
X+}
X+
X+static u8 INB(int port)
X+{
X+ usleep(10);
X+ return inb(port);
X+}
X+#define OUTW outw
X+#else ifdef __FreeBSD__
X+#include <machine/cpufunc.h>
X+void OUTB(u8 v, unsigned int port)
X+{
X+ outb(port,v);
X+}
X+void OUTW(u16 v, unsigned int port)
X+{
X+ outw(port,v);
X+}
X+
X+static u8 INB(unsigned int port)
X+{
X+ usleep(10);
X+ return inb(port);
X+}
X+static int deviofd=-1;
X+int iopl(int lvl)
X+{
X+ if(lvl==0){
X+ if(deviofd!=-1){
X+ close(deviofd);
X+ deviofd=-1;
X+ }
X+ return 0;
X+ }else if(lvl==3){
X+ if(deviofd==-1){
X+ deviofd=open("/dev/io",0);
X+ }
X+ return deviofd;
X+ }
X+ return -1;
X+}
X+
X+#endif
X+/* initialise the SPIC - this comes from the AML code in the ACPI bios */
X+static void spic_srs(int fd, u16 port1, u16 port2, u8 irq)
X+{
X+ u8 v;
X+ u16 v2;
X+
X+ pci_config_write_u16(fd, SPI_G10A, port1);
X+ pci_config_read_u8(fd, SPI_G10L, &v);
X+ v = (v & 0xF0) | (port1 ^ port2);
X+ pci_config_write_u8(fd, SPI_G10L, v);
X+
X+ v2 = inw(SPI_IRQ_PORT);
X+ v2 &= ~(0x3 << SPI_IRQ_SHIFT);
X+ v2 |= (irq << SPI_IRQ_SHIFT);
X+ OUTW(v2, SPI_IRQ_PORT);
X+
X+ pci_config_read_u8(fd, SPI_G10L, &v);
X+ v = (v & 0x1F) | 0xC0;
X+ pci_config_write_u8(fd, SPI_G10L, v);
X+}
X+
X+/* disable the SPIC - this comes from the AML code in the ACPI bios */
X+static void spic_dis(void)
X+{
X+ u8 v1;
X+ u16 v;
X+
X+ pci_config_read_u8(spic_fd, SPI_G10L, &v1);
X+ pci_config_write_u8(spic_fd, SPI_G10L, v1 & 0x3F);
X+
X+ v = inw(SPI_IRQ_PORT);
X+ v |= (0x3 << SPI_IRQ_SHIFT);
X+ OUTW(v, SPI_IRQ_PORT);
X+ close(spic_fd);
X+}
X+
X+
X+static void spic_settle(void)
X+{
X+ while (INB(SPIC_PORT2) & 2) usleep(1);
X+}
X+
X+static u8 spic_call1(u8 dev)
X+{
X+ u8 v1, v2;
X+ spic_settle();
X+
X+ OUTB(dev, SPIC_PORT2);
X+ v1 = INB(SPIC_PORT2);
X+ v2 = INB(SPIC_PORT1);
X+ if (debug)
X+ printf("spic call1(%x) -> %x %x\n", dev, v1, v2);
X+ return v2;
X+}
X+
X+static u8 spic_call2(u8 dev, u8 fn)
X+{
X+ u8 v1;
X+
X+ while (INB(SPIC_PORT2) & 2) ;
X+ OUTB(dev, SPIC_PORT2);
X+
X+ while (INB(SPIC_PORT2) & 2) ;
X+ OUTB(fn, SPIC_PORT1);
X+
X+ v1 = INB(SPIC_PORT1);
X+ if (debug)
X+ printf("spic call2(%x, %x) -> %x\n", dev, fn, v1);
X+ return v1;
X+}
X+
X+static u8 spic_call3(u8 dev, u8 fn, u8 v)
X+{
X+ u8 v1;
X+
X+ while (INB(SPIC_PORT2) & 2) ;
X+ OUTB(dev, SPIC_PORT2);
X+
X+ while (INB(SPIC_PORT2) & 2) ;
X+ OUTB(fn, SPIC_PORT1);
X+
X+ while (INB(SPIC_PORT2) & 2) ;
X+ OUTB(v, SPIC_PORT1);
X+
X+ v1 = INB(SPIC_PORT1);
X+ if (debug)
X+ printf("call3(%x, %x, %x) -> %x\n", dev, fn, v, v1);
X+ return v1;
X+}
X+
X+static u8 spic_read(u8 fn)
X+{
X+ u8 v1, v2;
X+ int n = 100;
X+ while (n--) {
X+ v1 = spic_call2(0x8f, fn);
X+ v2 = spic_call2(0x8f, fn);
X+ if (v1 == v2 && v1 != 0xff) {
X+ return v1;
X+ }
X+ }
X+ return 0xff;
X+}
X+
X+/* set brightness, hue etc */
X+static void spic_set(u8 fn, u8 v)
X+{
X+ int n = 100;
X+ while (n--) {
X+ if (spic_call3(0x90, fn, v) == 0) break;
X+ }
X+}
X+
X+static int spic_camera_ready(void)
X+{
X+ u8 v = spic_call2(0x8f, SPIC_CAMERA_STATUS);
X+ return (v != 0xff && (v & SPIC_CAMERA_STATUS_READY));
X+}
X+
X+/* turn the camera off */
X+void spic_camera_off(void)
X+{
X+ spic_call2(0x91, 0);
X+}
X+
X+/* turn the camera on */
X+void spic_camera_on(void)
X+{
X+ int i;
X+
X+ while (spic_call2(0x91, 0x1) != 0) usleep(1);
X+ spic_call1(0x93);
X+
X+ if (!spic_camera_ready()) {
X+ printf("waiting for camera ready\n");
X+ for (i=400;i>0;i--) {
X+ if (spic_camera_ready()) break;
X+ usleep(100);
X+ }
X+ if (i == 0) {
X+ printf("failed to power on camera\n");
X+ return;
X+ }
X+ }
X+
X+ spic_set(0x10, 0x5a);
X+}
X+
X+/* return 0 if capture not pressed, return 1 if pressed to partial,
X+ return 2 if fully pressed */
X+int spic_capture_pressed(void)
X+{
X+ u8 v1, v2;
X+ v1 = inb(SPIC_PORT1);
X+ v2 = inb(SPIC_PORT2);
X+ if (v2 != 0x60) return 0;
X+ if (v1 == SPIC_EVENT_CAPTURE_PARTIAL) return 1;
X+ if (v1 == SPIC_EVENT_CAPTURE_FULL) return 2;
X+ return 0;
X+}
X+
X+int spic_jogger_pressed(void)
X+{
X+ u8 v1, v2;
X+ v1 = inb(SPIC_PORT1);
X+ v2 = inb(SPIC_PORT2);
X+ return (v1 == 0x40 && v2 == 0x10);
X+}
X+
X+int spic_jogger_turned(void)
X+{
X+ u8 v1, v2;
X+ v1 = inb(SPIC_PORT1);
X+ v2 = inb(SPIC_PORT2);
X+ if ((v2 & 0x10) == 0 || v1 == 0) return 0;
X+ /* the following clears the evnet bits */
X+ spic_call2(0x81, 0xff);
X+ return (signed char)v1;
X+}
X+
X+int spic_jogger(void)
X+{
X+ u8 v1, v2, ov1=0, ov2=1;
X+ while (1) {
X+ v1 = INB(SPIC_PORT1);
X+ v2 = INB(SPIC_PORT2);
X+ if (v1 != ov1 || v2 != ov2) {
X+ printf("event 0x%02x 0x%02x\n", v1, v2);
X+ }
X+ ov1 = v1;
X+ ov2 = v2;
X+ }
X+}
X+
X+void spic_settings(int brightness, int contrast, int hue, int color, int sharpness, int picture, int agc)
X+{
X+ spic_set(SPIC_CAMERA_BRIGHTNESS, brightness);
X+ spic_set(SPIC_CAMERA_CONTRAST, contrast);
X+ spic_set(SPIC_CAMERA_HUE, hue);
X+ spic_set(SPIC_CAMERA_COLOR, color);
X+ spic_set(SPIC_CAMERA_SHARPNESS, sharpness);
X+ spic_set(SPIC_CAMERA_PICTURE, picture);
X+ spic_set(SPIC_CAMERA_AGC, agc);
X+}
X+
X+void spic_setup_vga(void)
X+{
X+/* :about to start capture again
*/
X+OUTB(0x09, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000026 */
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTB(0x0A, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000021 */
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00000020 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 000000F3 */
X+OUTW(0x2008, 0x03C4); usleep(10);
X+OUTW(0xF309, 0x03C4); usleep(10);
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x09, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000026 */
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTB(0x0A, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000021 */
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00000020 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 000000F3 */
X+OUTW(0xF109, 0x03C4); usleep(10);
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x09, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000026 */
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTB(0x0A, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000021 */
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00000020 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 0000001F */
X+OUTW(0x1D09, 0x03C4); usleep(10);
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00002621 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 000026E9 */
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00002621 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 000026F9 */
X+OUTB(0x09, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000026 */
X+OUTB(0x09, 0x03CE); usleep(10);
X+OUTB(0x26, 0x03CF); usleep(10);
X+OUTB(0x0A, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000021 */
X+OUTB(0x0A, 0x03CE); usleep(10);
X+OUTB(0x21, 0x03CF); usleep(10);
X+OUTB(0x0F, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00000001 */
X+OUTB(0x0F, 0x03C4); usleep(10);
X+OUTB(0x01, 0x03C5); usleep(10);
X+OUTB(0x0F, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00000001 */
X+OUTB(0x0A, 0x03CE); usleep(10);
X+OUTB(0x21, 0x03CF); usleep(10);
X+OUTB(0x09, 0x03CE); usleep(10);
X+OUTB(0x26, 0x03CF); usleep(10);
X+OUTB(0x09, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000026 */
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTB(0xBF, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000000 */
X+OUTB(0xA3, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 0000000C */
X+OUTW(0xBF, 0x03CE); usleep(10);
X+OUTW(0x0CA3, 0x03CE); usleep(10);
X+OUTB(0x09, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000026 */
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTB(0x0A, 0x03CE); usleep(10);
X+inb(0x03CF); usleep(10); /* -> 00000021 */
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00000021 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 000000F9 */
X+OUTW(0x2609, 0x03CE); usleep(10);
X+OUTW(0x210A, 0x03CE); usleep(10);
X+OUTB(0x08, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 00002621 */
X+OUTB(0x09, 0x03C4); usleep(10);
X+inb(0x03C5); usleep(10); /* -> 000026F9 */
X+}
X+
X+void spic_show_settings(void)
X+{
X+ printf("Brightness %d ", spic_read(SPIC_CAMERA_BRIGHTNESS));
X+ printf("Color %d ", spic_read(SPIC_CAMERA_COLOR));
X+ printf("Contrast %d ", spic_read(SPIC_CAMERA_CONTRAST));
X+ printf("Hue %d ", spic_read(SPIC_CAMERA_HUE));
X+ printf("Sharpness %d\n", spic_read(SPIC_CAMERA_SHARPNESS));
X+ printf("Picture 0x%02x ", spic_read(SPIC_CAMERA_PICTURE));
X+ printf("AGC 0x%02x ", spic_read(SPIC_CAMERA_AGC));
X+ printf("Direction: %s\n", (spic_read(SPIC_CAMERA_STATUS) & SPIC_DIRECTION_BACKWARDS) ? "back":"front");
X+ printf("RomVersion: %d ", spic_read(SPIC_CAMERA_ROMVERSION));
X+ printf("Revision: %d\n", spic_read(SPIC_CAMERA_REVISION));
X+}
X+
X+void spic_init(void)
X+{
X+ spic_fd = pci_find_device(SPIC_PCI_VENDOR, SPIC_PCI_DEVICE);
X+ if (spic_fd == -1) {
X+ printf("can't find spic PCI device\n");
X+ exit(1);
X+ }
X+
X+ iopl(3);
X+ spic_srs(spic_fd, SPIC_PORT1, SPIC_PORT2, 0x3);
X+
X+ spic_call1(0x82);
X+ spic_call2(0x81, 0xff);
X+ spic_call1(0x92);
X+
X+// printf("spic enabled\n");
X+}
X+
X+void sdelay(u32 usecs)
X+{
X+ INB(SPIC_PORT1);
X+ INB(SPIC_PORT2);
X+ usleep(usecs);
X+}
X+
X+void spic_shutdown(int power_off)
X+{
X+ spic_set(SPIC_CAMERA_PICTURE, SPIC_CAMERA_MUTE_MASK);
X+ spic_call2(0x81, 0); /* make sure we don't get any more events */
X+ if (power_off) {
X+ spic_camera_off();
X+ printf("camera off\n");
X+ }
X+ spic_dis();
X+}
X+
X+
X+
X+
END-of-sjog/files/patch-src::sonypi.c
echo x - sjog/files/patch-src::sonypi.h
sed 's/^X//' >sjog/files/patch-src::sonypi.h << 'END-of-sjog/files/patch-src::sonypi.h'
X--- src/sonypi.h.orig Sat Aug 17 20:38:56 2002
X+++ src/sonypi.h Sat Aug 17 20:38:56 2002
X@@ -0,0 +1,84 @@
X+#include <stdio.h>
X+#include <stdlib.h>
X+#include <unistd.h>
X+#include <fcntl.h>
X+#include <errno.h>
X+#include <sys/mman.h>
X+#include <dirent.h>
X+#include <ctype.h>
X+#include <string.h>
X+#include <signal.h>
X+#include <sys/pciio.h>
X+#define O_SYNC O_FSYNC
X+#include <sys/stat.h>
X+#include <sys/time.h>
X+
X+typedef unsigned char u8;
X+typedef unsigned short u16;
X+typedef unsigned u32;
X+
X+#define PAGE_SIZE 0x1000
X+
X+#define SONYPI_DEV "/proc/bus/pci/00/07.3"
X+
X+#define SPIC_PCI_VENDOR 0x8086
X+#define SPIC_PCI_DEVICE 0x7113
X+
X+/* the irq selection is 2 bits in the following port */
X+#define SPI_IRQ_PORT 0x8034
X+#define SPI_IRQ_SHIFT 22
X+
X+#define SPI_BASE 0x50
X+
X+#define SPI_G10A (SPI_BASE+0x14)
X+#define SPI_G10L (SPI_BASE+0x16) /* 4 bits at this offset - the port offset of
X+ 2nd port from first */
X+#define SPIC_PORT1 0x10a0
X+#define SPIC_PORT2 0x10a4
X+
X+#define SPIC_CAMERA_BRIGHTNESS 0
X+#define SPIC_CAMERA_CONTRAST 1
X+#define SPIC_CAMERA_HUE 2
X+#define SPIC_CAMERA_COLOR 3
X+#define SPIC_CAMERA_SHARPNESS 4
X+
X+#define SPIC_CAMERA_PICTURE 5
X+#define SPIC_CAMERA_EXPOSURE_MASK 0xC
X+#define SPIC_CAMERA_WHITE_BALANCE_MASK 0x3
X+#define SPIC_CAMERA_PICTURE_MODE_MASK 0x30
X+#define SPIC_CAMERA_MUTE_MASK 0x40
X+
X+/* the rest don't need a loop until not 0xff */
X+#define SPIC_CAMERA_AGC 6
X+#define SPIC_CAMERA_AGC_MASK 0x30
X+#define SPIC_CAMERA_SHUTTER_MASK 0x7
X+
X+#define SPIC_CAMERA_SHUTDOWN_REQUEST 7
X+#define SPIC_CAMERA_CONTROL 0x10
X+
X+#define SPIC_CAMERA_STATUS 7
X+#define SPIC_CAMERA_STATUS_READY 0x2
X+#define SPIC_CAMERA_STATUS_POSITION 0x4
X+
X+#define SPIC_DIRECTION_BACKWARDS 0x4
X+
X+#define SPIC_CAMERA_REVISION 8
X+#define SPIC_CAMERA_ROMVERSION 9
X+
X+
X+#define SPIC_EVENT_CAPTURE_BUTTON 0x20
X+#define SPIC_EVENT_CAPTURE_PARTIAL 0x05
X+#define SPIC_EVENT_CAPTURE_FULL 0x07
X+
X+#define JOGGER_V1 0x1
X+#define JOGGER_V2 0x19
X+
X+#define BRIGHTNESS_V1 0x15
X+#define BRIGHTNESS_V2 0x29
X+
X+#define VOLUME_V1 0x14
X+#define VOLUME_V2 0x29
X+
X+#define MUTE_V1 0x13
X+#define MUTE_V2 0x29
X+
END-of-sjog/files/patch-src::sonypi.h
echo x - sjog/files/patch-setbrightness::Makefile.am
sed 's/^X//' >sjog/files/patch-setbrightness::Makefile.am << 'END-of-sjog/files/patch-setbrightness::Makefile.am'
X--- setbrightness/Makefile.am.orig Wed Apr 4 11:20:07 2001
X+++ setbrightness/Makefile.am Sat Aug 17 20:38:56 2002
X@@ -2,7 +2,9 @@
X
X bin_PROGRAMS = setbrightness
X
X-setbrightness_SOURCES = setbrightness.c
X+setbrightness_SOURCES = setbrightness.c
X+
X+LDADD = ../src/sonypi.o ../src/pci_freebsd.o
X
X MAINTAINERCLEANFILES = Makefile.in Makefile
X
END-of-sjog/files/patch-setbrightness::Makefile.am
echo x - sjog/files/patch-src::Makefile.am
sed 's/^X//' >sjog/files/patch-src::Makefile.am << 'END-of-sjog/files/patch-src::Makefile.am'
X--- src/Makefile.am.orig Fri Aug 3 08:29:27 2001
X+++ src/Makefile.am Sat Aug 17 20:43:55 2002
X@@ -28,7 +28,11 @@
X sjog_volume_callbacks.c \
X sjog_volume_callbacks.h \
X sjog_scroll.c \
X- sjog_scroll.h
X+ sjog_scroll.h \
X+ sonypi.h \
X+ sonypi.c \
X+ pci_freebsd.c \
X+ pci.h
X
X sjog_LDADD = @GTK_LIBS@ @GLIB_LIBS@ @X_LIBS@
X
END-of-sjog/files/patch-src::Makefile.am
echo x - sjog/distinfo
sed 's/^X//' >sjog/distinfo << 'END-of-sjog/distinfo'
XMD5 (sjog-0.5.tar.gz) = 54c79675e5feb4a16a97901f6c7c5677
END-of-sjog/distinfo
echo x - sjog/Makefile
sed 's/^X//' >sjog/Makefile << 'END-of-sjog/Makefile'
X# New ports collection makefile for: sjog
X# Date created: 17 August 2002
X# Whom: Bruce M Simpson <bms@spc.org>
X#
X# $FreeBSD$
X#
X
XPORTNAME= sjog
XPORTVERSION= 0.5
XCATEGORIES= sysutils
XMASTER_SITES= ${MASTER_SITE_SOURCEFORGE}
XMASTER_SITE_SUBDIR= ${PORTNAME}
X
XMAINTAINER= bms@spc.org
X
XUSE_AUTOMAKE= yes
XGNU_CONFIGURE= yes
XUSE_GTK= yes
XUSE_GMAKE= yes
X
XNOMAN=
X
X.include <bsd.port.mk>
END-of-sjog/Makefile
echo x - sjog/pkg-plist
sed 's/^X//' >sjog/pkg-plist << 'END-of-sjog/pkg-plist'
Xbin/sjog
Xbin/setbrightness
Xetc/sjogrc
Xshare/sjog/pixmaps/sjog-brightness.xpm
Xshare/sjog/pixmaps/sjog-volume.xpm
X@dirrm share/sjog/pixmaps
X@dirrm share/sjog
END-of-sjog/pkg-plist
echo x - sjog/pkg-comment
sed 's/^X//' >sjog/pkg-comment << 'END-of-sjog/pkg-comment'
XUserland daemon for Sony Vaio Jog Dial
END-of-sjog/pkg-comment
echo x - sjog/pkg-descr
sed 's/^X//' >sjog/pkg-descr << 'END-of-sjog/pkg-descr'
XFrom the website:
X
XS-Jog is a program that uses the Sony Vaio laptop's Jog Wheel to do
Xvarious things:
X
X * Launch applications
X * Adjust screen brightness
X * Adjust volume
X * Act like a mousewheel
X
XS-Jog pops up when you click the Jog Wheel then disappears after 3 seconds
Xof idle time. The mousewheel feature is turned on when S-Jog is hidden.
X
XWWW: http://sjog.sourceforge.net/
X
XBruce
Xbms@spc.org
END-of-sjog/pkg-descr
exit
--- sjog.shar ends here ---
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