From owner-svn-src-all@FreeBSD.ORG Thu Sep 4 01:04:38 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 20A20192; Thu, 4 Sep 2014 01:04:38 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id E7A2E1239; Thu, 4 Sep 2014 01:04:37 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s8414bBB079686; Thu, 4 Sep 2014 01:04:37 GMT (envelope-from yongari@FreeBSD.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s8414bar079685; Thu, 4 Sep 2014 01:04:37 GMT (envelope-from yongari@FreeBSD.org) Message-Id: <201409040104.s8414bar079685@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: yongari set sender to yongari@FreeBSD.org using -f From: Pyun YongHyeon Date: Thu, 4 Sep 2014 01:04:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r271073 - head/sys/dev/mii X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Sep 2014 01:04:38 -0000 Author: yongari Date: Thu Sep 4 01:04:37 2014 New Revision: 271073 URL: http://svnweb.freebsd.org/changeset/base/271073 Log: Do not blindly announce 1000baseT half-duplex capability in autonegotiation. Some controllers like cgem(4) do not support half-duplex at gigabit speeds. Modified: head/sys/dev/mii/e1000phy.c Modified: head/sys/dev/mii/e1000phy.c ============================================================================== --- head/sys/dev/mii/e1000phy.c Thu Sep 4 00:43:27 2014 (r271072) +++ head/sys/dev/mii/e1000phy.c Thu Sep 4 01:04:37 2014 (r271073) @@ -169,8 +169,12 @@ e1000phy_attach(device_t dev) PHY_RESET(sc); sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; - if (sc->mii_capabilities & BMSR_EXTSTAT) + if (sc->mii_capabilities & BMSR_EXTSTAT) { sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) + sc->mii_flags |= MIIF_HAVE_GTCR; + } device_printf(dev, " "); mii_phy_add_media(sc); printf("\n"); @@ -319,8 +323,7 @@ e1000phy_service(struct mii_softc *sc, s speed = 0; switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_1000_T: - if ((sc->mii_extcapabilities & - (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) + if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0) return (EINVAL); speed = E1000_CR_SPEED_1000; break; @@ -357,10 +360,9 @@ e1000phy_service(struct mii_softc *sc, s if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { gig |= E1000_1GCR_MS_ENABLE; - if ((ife->ifm_media & IFM_ETH_MASTER) != 0) + if ((ife->ifm_media & IFM_ETH_MASTER) != 0) gig |= E1000_1GCR_MS_VALUE; - } else if ((sc->mii_extcapabilities & - (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) + } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) gig = 0; PHY_WRITE(sc, E1000_1GCR, gig); PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); @@ -485,9 +487,14 @@ e1000phy_mii_phy_auto(struct mii_softc * PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); } else PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); - if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) - PHY_WRITE(sc, E1000_1GCR, - E1000_1GCR_1000T_FD | E1000_1GCR_1000T); + if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) { + reg = 0; + if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0) + reg |= E1000_1GCR_1000T_FD; + if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0) + reg |= E1000_1GCR_1000T; + PHY_WRITE(sc, E1000_1GCR, reg); + } PHY_WRITE(sc, E1000_CR, E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);