From owner-svn-src-head@FreeBSD.ORG Mon Apr 26 20:19:50 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2E8CE1065670; Mon, 26 Apr 2010 20:19:50 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 1C92D8FC17; Mon, 26 Apr 2010 20:19:50 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o3QKJo2n089974; Mon, 26 Apr 2010 20:19:50 GMT (envelope-from marius@svn.freebsd.org) Received: (from marius@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o3QKJnNO089968; Mon, 26 Apr 2010 20:19:49 GMT (envelope-from marius@svn.freebsd.org) Message-Id: <201004262019.o3QKJnNO089968@svn.freebsd.org> From: Marius Strobl Date: Mon, 26 Apr 2010 20:19:49 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r207248 - head/sys/sparc64/sparc64 X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Apr 2010 20:19:50 -0000 Author: marius Date: Mon Apr 26 20:19:49 2010 New Revision: 207248 URL: http://svn.freebsd.org/changeset/base/207248 Log: Don't bother enabling interrupts before we're ready to handle them. This prevents the firmware of Fujitsu Siemens PRIMEPOWER250, which both causes stray interrupts and erroneously enables interrupts at least when calling SUNW,set-trap-table, in the foot. Modified: head/sys/sparc64/sparc64/cheetah.c head/sys/sparc64/sparc64/locore.S head/sys/sparc64/sparc64/machdep.c head/sys/sparc64/sparc64/mp_locore.S head/sys/sparc64/sparc64/mp_machdep.c Modified: head/sys/sparc64/sparc64/cheetah.c ============================================================================== --- head/sys/sparc64/sparc64/cheetah.c Mon Apr 26 20:05:48 2010 (r207247) +++ head/sys/sparc64/sparc64/cheetah.c Mon Apr 26 20:19:49 2010 (r207248) @@ -58,13 +58,6 @@ void cheetah_init(u_int cpu_impl) { u_long val; - register_t s; - - /* - * Disable interrupts for safety, this shouldn't be actually - * necessary though. - */ - s = intr_disable(); /* Ensure the TSB Extension Registers hold 0 as TSB_Base. */ @@ -134,8 +127,6 @@ cheetah_init(u_int cpu_impl) val &= ~DCR_DTPE; } wr(asr18, val, 0); - - intr_restore(s); } /* Modified: head/sys/sparc64/sparc64/locore.S ============================================================================== --- head/sys/sparc64/sparc64/locore.S Mon Apr 26 20:05:48 2010 (r207247) +++ head/sys/sparc64/sparc64/locore.S Mon Apr 26 20:19:49 2010 (r207248) @@ -29,6 +29,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include @@ -47,7 +48,7 @@ ENTRY(btext) ENTRY(_start) /* * Initialize misc. state to known values: interrupts disabled, normal - * globals, windows flushed (cr = 0, cs = nwindows - 1), PIL 0 and + * globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and * floating point disabled. * Note that some firmware versions don't implement a clean window * trap handler so we unfortunately can't clear the windows by setting @@ -55,7 +56,7 @@ ENTRY(_start) */ wrpr %g0, PSTATE_NORMAL, %pstate flushw - wrpr %g0, 0, %pil + wrpr %g0, PIL_TICK, %pil wr %g0, 0, %fprs /* @@ -66,11 +67,6 @@ ENTRY(_start) sub %l0, SPOFF + CCFSZ, %sp /* - * Enable interrupts. - */ - wrpr %g0, PSTATE_KERNEL, %pstate - - /* * Do initial bootstrap to setup pmap and thread0. */ call sparc64_init @@ -97,7 +93,7 @@ ENTRY(cpu_setregs) ldx [%o0 + PC_CURPCB], %o1 /* - * Disable interrupts, normal globals. + * Ensure we are on normal globals. */ wrpr %g0, PSTATE_NORMAL, %pstate @@ -147,11 +143,6 @@ ENTRY(cpu_setregs) wrpr %o1, 0, %tba stw %o3, [%o2] - /* - * Re-enable interrupts. - */ - wrpr %g0, PSTATE_KERNEL, %pstate - retl nop END(cpu_setregs) Modified: head/sys/sparc64/sparc64/machdep.c ============================================================================== --- head/sys/sparc64/sparc64/machdep.c Mon Apr 26 20:05:48 2010 (r207247) +++ head/sys/sparc64/sparc64/machdep.c Mon Apr 26 20:19:49 2010 (r207248) @@ -341,7 +341,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_l cpu_impl = VER_IMPL(rdpr(ver)); /* - * Do CPU-specific Initialization. + * Do CPU-specific initialization. */ if (cpu_impl >= CPU_IMPL_ULTRASPARCIII) cheetah_init(cpu_impl); @@ -477,6 +477,10 @@ sparc64_init(caddr_t mdp, u_long o1, u_l sizeof(itlb_slots)) == -1) panic("sparc64_init: cannot determine number of iTLB slots"); + /* + * Initialize and enable the caches. Note that his may include + * applying workarounds. + */ cache_init(pc); cache_enable(cpu_impl); uma_set_align(pc->pc_cache.dc_linesize - 1); @@ -568,8 +572,18 @@ sparc64_init(caddr_t mdp, u_long o1, u_l dpcpu_init(dpcpu0, 0); msgbufinit(msgbufp, MSGBUF_SIZE); + /* + * Initialize mutexes. + */ mutex_init(); + + /* + * Finish the interrupt initialization now that mutexes work and + * enable them. + */ intr_init2(); + wrpr(pil, 0, PIL_TICK); + wrpr(pstate, 0, PSTATE_KERNEL); /* * Finish pmap initialization now that we're ready for mutexes. Modified: head/sys/sparc64/sparc64/mp_locore.S ============================================================================== --- head/sys/sparc64/sparc64/mp_locore.S Mon Apr 26 20:05:48 2010 (r207247) +++ head/sys/sparc64/sparc64/mp_locore.S Mon Apr 26 20:19:49 2010 (r207248) @@ -30,6 +30,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #include @@ -44,14 +45,14 @@ __FBSDID("$FreeBSD$"); _ALIGN_TEXT /* * Initialize misc. state to known values: interrupts disabled, normal - * globals, windows flushed (cr = 0, cs = nwindows - 1), PIL 0 and + * globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and * floating point disabled. * Note that some firmware versions don't implement a clean window * trap handler so we unfortunately can't clear the windows by setting * %cleanwin to zero here. */ 1: wrpr %g0, PSTATE_NORMAL, %pstate - wrpr %g0, 0, %pil + wrpr %g0, PIL_TICK, %pil wr %g0, 0, %fprs rdpr %ver, %l7 @@ -262,11 +263,6 @@ ENTRY(mp_startup) add %l1, %l2, %l1 sub %l1, SPOFF + CCFSZ, %sp - /* - * Enable interrupts. - */ - wrpr %g0, PSTATE_KERNEL, %pstate - #if KTR_COMPILE & KTR_SMP CATR(KTR_SMP, "mp_startup: bootstrap cpuid=%d mid=%d pcpu=%#lx data=%#lx sp=%#lx" Modified: head/sys/sparc64/sparc64/mp_machdep.c ============================================================================== --- head/sys/sparc64/sparc64/mp_machdep.c Mon Apr 26 20:05:48 2010 (r207247) +++ head/sys/sparc64/sparc64/mp_machdep.c Mon Apr 26 20:19:49 2010 (r207248) @@ -409,16 +409,32 @@ cpu_mp_bootstrap(struct pcpu *pc) volatile struct cpu_start_args *csa; csa = &cpu_start_args; + + /* Do CPU-specific initialization. */ if (pc->pc_impl >= CPU_IMPL_ULTRASPARCIII) cheetah_init(pc->pc_impl); + /* + * Enable the caches. Note that his may include applying workarounds. + */ cache_enable(pc->pc_impl); + + /* Lock the kernel TSB in the TLB. */ pmap_map_tsb(); + /* * Flush all non-locked TLB entries possibly left over by the * firmware. */ tlb_flush_nonlocked(); + + /* Initialize global registers. */ cpu_setregs(pc); + + /* Enable interrupts. */ + wrpr(pil, 0, PIL_TICK); + wrpr(pstate, 0, PSTATE_KERNEL); + + /* Start the (S)TICK interrupts. */ tick_start(); smp_cpus++;