Date: Mon, 15 Mar 1999 00:19:45 -0800 From: Mike Smith <mike@smith.net.au> To: Matthew Dillon <dillon@apollo.backplane.com> Cc: Bill Paul <wpaul@skynet.ctr.columbia.edu>, hackers@FreeBSD.ORG Subject: Re: Fifabit ethernet -- what am I doing wrong? Message-ID: <199903150819.AAA10739@dingo.cdrom.com> In-Reply-To: Your message of "Mon, 15 Mar 1999 00:20:34 PST." <199903150820.AAA96533@apollo.backplane.com>
next in thread | previous in thread | raw e-mail | index | archive | help
> :Okay, here's an update. I've been reading all the replies to this > :thread, but it turns out that my main problem is that, as expected, > :I was screwing something up. > : > :The Tigon has a PCI state register which lets you configure several > :aspects operation. Two of the parameters are PCI read max and PCI write > :max, which force termination of PCI reads or writes at a specified > :boundaries 4 bytes, 16, 32, 64, 128, 256, 1K. I had originally set > :the read and write max values for 32. It turns out that disabling > :these settings (by making them 0) yields _much_ better performance. > > 32 bytes is only 4 PCI clocks -- a serious waste of PCI burst > bandwidth. However, you should get good results with 128, 256, or > 1K. You don't want completely unlimited unless you don't mind > the card completely hogging the PCI bus for long periods of > time. It won't ever hog it for (much) longer than the PCI latency count; the arbiter will push it off the bus once the latency counter expires after someone else requests it. If the bus is relatively quiet, not re-cycling every few dozen cycles will improve things (a little). > :ring fast enough). Normally the Tigon has both the PCI read and write > :DMA channels active at the same time, but you can force only one to > :be active at a time by setting a bit in the operating mode register. > :The manual recommends _not_ doing this, but setting it yielded yet > :another jump in performance. > > That's very interesting. Perhaps it is trying to interleave read > and write requests and is blowing the burst transfers in so doing. > You ought to be able to mess around with the burst length such > that you can leave the DMA set for simultaniously-enabled > operation. I'd guess that it may only have a single PCI FIFO in the bridge, and it has to drain/fill it as it turns around. That'd certainly hurt. -- \\ Sometimes you're ahead, \\ Mike Smith \\ sometimes you're behind. \\ mike@smith.net.au \\ The race is long, and in the \\ msmith@freebsd.org \\ end it's only with yourself. \\ msmith@cdrom.com To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199903150819.AAA10739>