From owner-svn-src-all@FreeBSD.ORG Fri Aug 13 12:56:00 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A090210656A4; Fri, 13 Aug 2010 12:56:00 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 8CEF18FC1C; Fri, 13 Aug 2010 12:56:00 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o7DCu09X006920; Fri, 13 Aug 2010 12:56:00 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o7DCu0lS006909; Fri, 13 Aug 2010 12:56:00 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201008131256.o7DCu0lS006909@svn.freebsd.org> From: "Jayachandran C." Date: Fri, 13 Aug 2010 12:56:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r211280 - in head/sys: conf mips/conf mips/include mips/mips mips/rmi X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Aug 2010 12:56:00 -0000 Author: jchandra Date: Fri Aug 13 12:56:00 2010 New Revision: 211280 URL: http://svn.freebsd.org/changeset/base/211280 Log: Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions. use CPU_RMI all XLR configurations. Update ident string for N32 and N64 kernels. Modified: head/sys/conf/options.mips head/sys/mips/conf/XLR head/sys/mips/conf/XLR64 head/sys/mips/conf/XLRN32 head/sys/mips/include/bus.h head/sys/mips/include/intr_machdep.h head/sys/mips/mips/exception.S head/sys/mips/mips/locore.S head/sys/mips/mips/machdep.c head/sys/mips/rmi/std.xlr Modified: head/sys/conf/options.mips ============================================================================== --- head/sys/conf/options.mips Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/conf/options.mips Fri Aug 13 12:56:00 2010 (r211280) @@ -35,6 +35,7 @@ CPU_SENTRY5 opt_global.h CPU_HAVEFPU opt_global.h CPU_SB1 opt_global.h CPU_CNMIPS opt_global.h +CPU_RMI opt_global.h ISA_MIPS1 opt_cputype.h ISA_MIPS3 opt_cputype.h @@ -51,7 +52,6 @@ CFE_ENV_SIZE opt_global.h NOFPU opt_global.h TARGET_EMULATOR opt_ddb.h -TARGET_XLR_XLS opt_global.h TICK_USE_YAMON_FREQ opt_global.h TICK_USE_MALTA_RTC opt_global.h Modified: head/sys/mips/conf/XLR ============================================================================== --- head/sys/mips/conf/XLR Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/conf/XLR Fri Aug 13 12:56:00 2010 (r211280) @@ -46,7 +46,7 @@ # $FreeBSD$ machine mips -cpu CPU_MIPS4KC +cpu CPU_RMI ident XLR makeoptions MODULES_OVERRIDE="" Modified: head/sys/mips/conf/XLR64 ============================================================================== --- head/sys/mips/conf/XLR64 Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/conf/XLR64 Fri Aug 13 12:56:00 2010 (r211280) @@ -18,8 +18,8 @@ # $FreeBSD$ machine mips -cpu CPU_MIPS4KC -ident XLR +cpu CPU_RMI +ident XLR64 makeoptions MODULES_OVERRIDE="" makeoptions TARGET_BIG_ENDIAN Modified: head/sys/mips/conf/XLRN32 ============================================================================== --- head/sys/mips/conf/XLRN32 Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/conf/XLRN32 Fri Aug 13 12:56:00 2010 (r211280) @@ -18,8 +18,8 @@ # $FreeBSD$ machine mips -cpu CPU_MIPS4KC -ident XLR +cpu CPU_RMI +ident XLRN32 makeoptions MODULES_OVERRIDE="" makeoptions TARGET_BIG_ENDIAN Modified: head/sys/mips/include/bus.h ============================================================================== --- head/sys/mips/include/bus.h Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/include/bus.h Fri Aug 13 12:56:00 2010 (r211280) @@ -721,7 +721,7 @@ void __bs_c(f,_bs_c_8) (void *t, bus_spa DECLARE_BUS_SPACE_PROTOTYPES(generic); extern bus_space_tag_t mips_bus_space_generic; /* Special bus space for RMI processors */ -#ifdef TARGET_XLR_XLS +#ifdef CPU_RMI extern bus_space_tag_t rmi_bus_space; extern bus_space_tag_t rmi_pci_bus_space; #endif Modified: head/sys/mips/include/intr_machdep.h ============================================================================== --- head/sys/mips/include/intr_machdep.h Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/include/intr_machdep.h Fri Aug 13 12:56:00 2010 (r211280) @@ -29,7 +29,7 @@ #ifndef _MACHINE_INTR_MACHDEP_H_ #define _MACHINE_INTR_MACHDEP_H_ -#ifdef TARGET_XLR_XLS +#ifdef CPU_RMI #define XLR_MAX_INTR 64 #else #define NHARD_IRQS 6 Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/mips/exception.S Fri Aug 13 12:56:00 2010 (r211280) @@ -243,7 +243,7 @@ SlowFault: and a0, a0, a2 ; \ mtc0 a0, MIPS_COP_0_STATUS ; \ ITLBNOPFIX -#elif defined(TARGET_XLR_XLS) +#elif defined(CPU_RMI) #define CLEAR_STATUS \ mfc0 a0, MIPS_COP_0_STATUS ;\ li a2, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) ; \ @@ -485,7 +485,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS3_SR_KSU_MASK | MIPS_SR_INT_IE) #if defined(CPU_CNMIPS) or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX) -#elif defined(TARGET_XLR_XLS) +#elif defined(CPU_RMI) or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) #endif mtc0 t0, MIPS_COP_0_STATUS @@ -703,7 +703,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS3_SR_KSU_MASK) #ifdef CPU_CNMIPS or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX) -#elif defined(TARGET_XLR_XLS) +#elif defined(CPU_RMI) or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) #endif mtc0 t0, MIPS_COP_0_STATUS Modified: head/sys/mips/mips/locore.S ============================================================================== --- head/sys/mips/mips/locore.S Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/mips/locore.S Fri Aug 13 12:56:00 2010 (r211280) @@ -99,7 +99,7 @@ VECTOR(_locore, unknown) /* Reset these bits */ li t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE) -#elif defined (TARGET_XLR_XLS) +#elif defined (CPU_RMI) /* Set these bits */ li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX | MIPS_SR_UX) Modified: head/sys/mips/mips/machdep.c ============================================================================== --- head/sys/mips/mips/machdep.c Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/mips/machdep.c Fri Aug 13 12:56:00 2010 (r211280) @@ -334,7 +334,7 @@ mips_vector_init(void) bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); -#if defined(CPU_CNMIPS) || defined(TARGET_XLR_XLS) +#if defined(CPU_CNMIPS) || defined(CPU_RMI) /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */ bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); Modified: head/sys/mips/rmi/std.xlr ============================================================================== --- head/sys/mips/rmi/std.xlr Fri Aug 13 11:24:02 2010 (r211279) +++ head/sys/mips/rmi/std.xlr Fri Aug 13 12:56:00 2010 (r211280) @@ -4,7 +4,4 @@ files "../rmi/files.xlr" # # XXXMIPS: It's a stub, isn't it? # -cpu CPU_MIPS4KC option NOFPU -# Kludge for now -options TARGET_XLR_XLS