From owner-svn-src-head@freebsd.org Thu Sep 1 14:58:12 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id A8CC2BCBDDA; Thu, 1 Sep 2016 14:58:12 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 6BE40C09; Thu, 1 Sep 2016 14:58:12 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u81EwBhG017781; Thu, 1 Sep 2016 14:58:11 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u81EwB6v017778; Thu, 1 Sep 2016 14:58:11 GMT (envelope-from br@FreeBSD.org) Message-Id: <201609011458.u81EwB6v017778@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Thu, 1 Sep 2016 14:58:11 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r305208 - in head/sys: boot/fdt/dts/riscv riscv/riscv X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Sep 2016 14:58:12 -0000 Author: br Date: Thu Sep 1 14:58:11 2016 New Revision: 305208 URL: https://svnweb.freebsd.org/changeset/base/305208 Log: o Separate rtc and timecmp registers: they are different across RISC-V cpu implementations. o Update RocketChip device tree source (DTS). We now support latest verison of RocketChip synthesized on Xilinx FPGA (Zedboard). RocketChip is an implementation of RISC-V processor written on Chisel hardware construction language. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/boot/fdt/dts/riscv/rocket.dts head/sys/boot/fdt/dts/riscv/spike.dts head/sys/riscv/riscv/timer.c Modified: head/sys/boot/fdt/dts/riscv/rocket.dts ============================================================================== --- head/sys/boot/fdt/dts/riscv/rocket.dts Thu Sep 1 14:57:06 2016 (r305207) +++ head/sys/boot/fdt/dts/riscv/rocket.dts Thu Sep 1 14:58:11 2016 (r305208) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2016 Ruslan Bukin + * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -37,8 +37,8 @@ /dts-v1/; / { - model = "UC Berkeley Spike Simulator RV64I"; - compatible = "riscv,rv64i"; + model = "RocketChip RV64"; + compatible = "riscv,rv64"; #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <1>; @@ -49,8 +49,8 @@ cpu@0 { device_type = "cpu"; - compatible = "riscv,rv64i"; - reg = <0x40002000>; + compatible = "riscv,rv64"; + reg = <0x0>; }; }; @@ -59,13 +59,17 @@ }; memory { + /* + * This is not used currently. + * We take information from sbi_query_memory. + */ device_type = "memory"; - reg = <0x0 0x10000000>; /* 256MB at 0x0 */ + reg = <0x80000000 0x10000000>; /* 256MB at 0x80000000 */ }; soc { - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; #interrupt-cells = <1>; compatible = "simple-bus"; @@ -78,7 +82,9 @@ timer0: timer@0 { compatible = "riscv,timer"; - interrupts = < 1 >; + reg = < 0x4400bff8 0x0008 >, /* rtc */ + < 0x44004000 0x1000 >; /* timecmp */ + interrupts = < 5 >; interrupt-parent = < &pic0 >; clock-frequency = < 1000000 >; }; Modified: head/sys/boot/fdt/dts/riscv/spike.dts ============================================================================== --- head/sys/boot/fdt/dts/riscv/spike.dts Thu Sep 1 14:57:06 2016 (r305207) +++ head/sys/boot/fdt/dts/riscv/spike.dts Thu Sep 1 14:58:11 2016 (r305208) @@ -50,13 +50,13 @@ cpu@0 { device_type = "cpu"; compatible = "riscv,rv64"; - reg = <0x40001000>; + reg = <0x0>; }; cpu@1 { device_type = "cpu"; compatible = "riscv,rv64"; - reg = <0x40002000>; + reg = <0x0>; }; }; @@ -88,7 +88,8 @@ timer0: timer@0 { compatible = "riscv,timer"; - reg = < 0x40000000 0x100 >; + reg = < 0x40000000 0x0008 >, /* rtc */ + < 0x40000008 0x1000 >; /* timecmp */ interrupts = < 5 >; interrupt-parent = < &pic0 >; clock-frequency = < 1000000 >; Modified: head/sys/riscv/riscv/timer.c ============================================================================== --- head/sys/riscv/riscv/timer.c Thu Sep 1 14:57:06 2016 (r305207) +++ head/sys/riscv/riscv/timer.c Thu Sep 1 14:58:11 2016 (r305208) @@ -69,7 +69,7 @@ __FBSDID("$FreeBSD$"); #define DEFAULT_FREQ 1000000 #define TIMER_COUNTS 0x00 -#define TIMER_MTIMECMP(cpu) (0x08 + (cpu * 8)) +#define TIMER_MTIMECMP(cpu) (cpu * 8) #define READ8(_sc, _reg) \ bus_space_read_8(_sc->bst, _sc->bsh, _reg) @@ -77,9 +77,11 @@ __FBSDID("$FreeBSD$"); bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val) struct riscv_tmr_softc { - struct resource *res[2]; + struct resource *res[3]; bus_space_tag_t bst; bus_space_handle_t bsh; + bus_space_tag_t bst_timecmp; + bus_space_handle_t bsh_timecmp; void *ih; uint32_t clkfreq; struct eventtimer et; @@ -89,6 +91,7 @@ static struct riscv_tmr_softc *riscv_tmr static struct resource_spec timer_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_MEMORY, 1, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; @@ -107,8 +110,11 @@ static struct timecounter riscv_tmr_time static long get_counts(struct riscv_tmr_softc *sc) { + uint64_t counts; + + counts = READ8(sc, TIMER_COUNTS); - return (READ8(sc, TIMER_COUNTS)); + return (counts); } static unsigned @@ -134,7 +140,8 @@ riscv_tmr_start(struct eventtimer *et, s counts = ((uint32_t)et->et_frequency * first) >> 32; counts += READ8(sc, TIMER_COUNTS); cpu = PCPU_GET(cpuid); - WRITE8(sc, TIMER_MTIMECMP(cpu), counts); + bus_space_write_8(sc->bst_timecmp, sc->bsh_timecmp, + TIMER_MTIMECMP(cpu), counts); csr_set(sie, SIE_STIE); sbi_set_timer(counts); @@ -225,11 +232,13 @@ riscv_tmr_attach(device_t dev) /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); + sc->bst_timecmp = rman_get_bustag(sc->res[1]); + sc->bsh_timecmp = rman_get_bushandle(sc->res[1]); riscv_tmr_sc = sc; /* Setup IRQs handler */ - error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, + error = bus_setup_intr(dev, sc->res[2], INTR_TYPE_CLK, riscv_tmr_intr, NULL, sc, &sc->ih); if (error) { device_printf(dev, "Unable to alloc int resource.\n");