From owner-svn-src-all@FreeBSD.ORG Sat Jul 28 11:09:03 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id C8823106564A; Sat, 28 Jul 2012 11:09:03 +0000 (UTC) (envelope-from rwatson@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 995168FC0C; Sat, 28 Jul 2012 11:09:03 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q6SB93O1019080; Sat, 28 Jul 2012 11:09:03 GMT (envelope-from rwatson@svn.freebsd.org) Received: (from rwatson@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q6SB93Qv019078; Sat, 28 Jul 2012 11:09:03 GMT (envelope-from rwatson@svn.freebsd.org) Message-Id: <201207281109.q6SB93Qv019078@svn.freebsd.org> From: Robert Watson Date: Sat, 28 Jul 2012 11:09:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r238861 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Jul 2012 11:09:03 -0000 Author: rwatson Date: Sat Jul 28 11:09:03 2012 New Revision: 238861 URL: http://svn.freebsd.org/changeset/base/238861 Log: Merge FreeBSD/beri Perforce change @211945 to head: Modify MIPS page table entry (PTE) initialisation so that cachability bits are set only once, using is_cacheable_mem() to determine what caching properties are required, rather than also unconditionally setting PTE_C_CACHE in init_pte_prot(). As PTE_C_CACHE | PTE_C_UNCACHED == PTE_C_CACHE, this meant that all userspace memory mappings of device memory (incorrectly) used caching TLB entries. This is arguably not quite what we want, even though it is (more) consistent with the MIPS pmap design: PTE caching properties should be derived from machine-independent page table attributes, but this is a substantially more complex change as the MIPS pmap doesn't yet know about page attributes, causing it to ignore requests by device drivers that want uncached userspace memory mappings as they describe memory-mapped FIFOs or shared memory with a device not participating in the cache coherence scheme. This fixes cacheability issues (specifically, undesired and unrequested caching) seen in userspace memory mappings of Avalon SoC bus device memory on BERI MIPS. Discussed with: jmallett, alc Sponsored by: DARPA, AFRL MFC after: 3 days Modified: head/sys/mips/mips/pmap.c Modified: head/sys/mips/mips/pmap.c ============================================================================== --- head/sys/mips/mips/pmap.c Sat Jul 28 07:56:23 2012 (r238860) +++ head/sys/mips/mips/pmap.c Sat Jul 28 11:09:03 2012 (r238861) @@ -3146,16 +3146,16 @@ init_pte_prot(vm_offset_t va, vm_page_t pt_entry_t rw; if (!(prot & VM_PROT_WRITE)) - rw = PTE_V | PTE_RO | PTE_C_CACHE; + rw = PTE_V | PTE_RO; else if ((m->oflags & VPO_UNMANAGED) == 0) { if ((m->md.pv_flags & PV_TABLE_MOD) != 0) - rw = PTE_V | PTE_D | PTE_C_CACHE; + rw = PTE_V | PTE_D; else - rw = PTE_V | PTE_C_CACHE; + rw = PTE_V; vm_page_aflag_set(m, PGA_WRITEABLE); } else /* Needn't emulate a modified bit for unmanaged pages. */ - rw = PTE_V | PTE_D | PTE_C_CACHE; + rw = PTE_V | PTE_D; return (rw); }