From owner-freebsd-current  Mon Dec  3 22:20: 2 2001
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From: Søren Schmidt <sos@freebsd.dk>
Message-Id: <200112040619.fB46Jd786535@freebsd.dk>
Subject: Re: HEADSUP ATA support for newer SiS chipsets added
In-Reply-To: <200112032214.fB3MEst98950@apollo.backplane.com>
To: Matthew Dillon <dillon@apollo.backplane.com>
Date: Tue, 4 Dec 2001 07:19:39 +0100 (CET)
Cc: nuzrin@goose.net.my, Miklos Niedermayer <mico@bsd.hu>,
	Greg Lehey <grog@FreeBSD.ORG>, current@FreeBSD.ORG
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It seems Matthew Dillon wrote:
> :Hmm, I've just played around a bit, it seems we are hit by interrupt
> :latency or something, if you limit the transfer to 128k, which allows
> :the ATA controller to fetch it in one go, you will see the expected
> :transfer rates. Now I dont see this on PCI based controllers, and that
> :hints that the problem could be the fact that the two onboard controllers
> :sits on irq 14 & 15 making them the lowest priority devices in the system,
> :and that could cause the interrupt latency I'm seeing which then again
> :causes the bad transfer rates on transfers that need to transfer more
> :that one transaction full of data (ie max 128k).
> :
> :-Søren
> 
>     The larger transfers are probably choking the IDE drive's pipelining
>     capabilities.  That's my guess, anyway.  I avoid IDE like the plague.

No, not true, if the same drive is put on a PCI based ATA controller
you get the expected transfer speed upto the drives cache size.

-Søren

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